SPI/

Digital

DIAG

BIAS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

AMX_OUT

DGND1

AGND1

SQREF1

SQREF2

VADC

TEST2

VA2

TEST2

GND1

ZM1

Z1

VZ1

ZM4

Z4

Z7

ZM7

VZ3

Z3

ZM3

GND3

DGND2

SOMI

SOMO

SCLK

CS_N

TZ0

RESET_N

VDDIO

AGND

VA1

TEST4

NC

GND2

ZM2

Z2

VZ2

ZM5

Z5

GND0

Z6

GND3

Z6

squib

squib

Z6

ZM6

VZ0

Z0

ZM0

GND0

TEST1

VCC5

IWD

squib

squib

squib

squib

squib

squib

squib

GND2

Z5

Z4

GND1

TPIC71008-Q1

www.ti.com

SLVSAX3

– JUNE 2011

Table 2. Potential Deployment Settings for Maximum Firing Current

MAXIMUM AVERAGE FIRING

FIRING

MAX FIRING

DWELL

VOLTAGE BETWEEN VZX AND ZX

VOLTAGE

(FIRING)TIME

PINS TO ACHIEVE DEPLOYMENT

2.6 A

35 V

30 V

(for 1.75 A current setting)

2. 0 A

35 V

31 V

(for 1.2 A current setting)

(1)

The max firing current levels are set through device EEPROM setting

(2)

For programming desired dwell (firing) time

Figure 1. Functional Block Diagram

For the full version of this document, please contact msamktg@list.ti.com .

Copyright

© 2011, Texas Instruments Incorporated

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