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KMB-001CEVALZ 데이터시트(PDF) 1 Page - Intersil Corporation

부품명 KMB-001CEVALZ
상세설명  High Performance Dual 14-Bit, 125MSPS ADC
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제조업체  INTERSIL [Intersil Corporation]
홈페이지  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

KMB-001CEVALZ 데이터시트(HTML) 1 Page - Intersil Corporation

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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|Copyright Intersil Americas Inc. 2012. All Rights Reserved
Intersil (and design) and FemtoCharge are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
High Performance Dual 14-Bit, 125MSPS ADC
ISLA224P12
The ISLA224P12 is a high performance dual 14-bit 125MSPS
analog-to-digital converter offering very high dynamic range and
low power consumption. It carries the export control
classification number 3A991.c.3 and can be exported without a
license to most countries, including China and Russia. It is part of
a pin-compatible family of 12- to 16-bit A/Ds with maximum
sample rates ranging from 125 to 500MSPS. This allows a design
using the ISLA224P12 to accommodate any of the other
pin-compatible A/Ds with minimal changes.
The ISLA224P12 is very flexible and can be designed into a wide
variety of systems. A serial peripheral interface (SPI) port allows
access to its extensive configurability as well as provides digital
control over various analog parameters such as input gain and
offset. Digital output data is presented in selectable LVDS or
CMOS formats in half-width, double data rate (DDR). Operating
from a 1.8V supply, performance is specified over the full
industrial temperature range (-40°C to +85°C).
Applications
• Radar Array Processing
•Software Defined Radio
• Broadband Communications
• High Performance Data Acquisition
• Communications Test Equipment
Features
• License-free Import for most countries including China and
Russia (ECCN 3A991.c.3)
•Multi-ADC Support
- SPI Programmable Fine Gain and Offset Control
- Multiple ADC Synchronization
- Optimized Output Timing
• Clock Duty Cycle Stabilizer
• Nap and Sleep Modes
• Programmable Built-in Test Patterns
• DDR LVDS-Compatible or LVCMOS Outputs
• Data Output Clock
Key Specifications
• SNR @ 125MSPS
-74.7dBFS fIN= 30MHz
- 70.2dBFS fIN = 363MHz
•SFDR @ 125MSPS
- 86dBc fIN = 30MHz
- 79dBc fIN = 363MHz
• Total Power Consumption = 590mW
DIGITAL
ERROR
CORRECTION
SHA
1.25V
VINBP
VINBN
14-BIT
125 MSPS
ADC
CLOCK
MANAGEMENT
SHA
14-BIT
125 MSPS
ADC
CLKP
CLKN
SPI
CONTROL
VREF
CLKOUTP
CLKOUTN
D[13:0]P
D[13:0]N
ORP
ORN
OUTFMT
OUTMODE
+
VCM
VREF
VINAN
VINAP
+
-
Pin-Compatible Family
MODEL
RESOLUTION
SPEED
(MSPS)
ISLA224P25
14
250
ISLA224P20
14
200
ISLA224P13
14
130
ISLA222P25
12
250
ISLA222P20
12
200
ISLA222P13
12
130
August 17, 2012
FN7983.3


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