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CDCE913PWG4 데이터시트(PDF) 5 Page - Texas Instruments |
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CDCE913PWG4 데이터시트(HTML) 5 Page - Texas Instruments |
5 / 26 page CDCE913 CDCEL913 www.ti.com SCAS849E – JUNE 2007 – REVISED MARCH 2010 TIMING REQUIREMENTS over recommended ranges of supply voltage, load, and operating free-air temperature MIN NOM MAX UNIT CLK_IN REQUIREMENTS PLL bypass mode 0 160 fCLK LVCMOS clock input frequency MHz PLL mode 8 160 tr / tf Rise and fall time CLK signal (20% to 80%) 3 ns Duty cycle CLK at VDD/2 40% 60% STANDARD FAST MODE MODE UNIT MIN MAX MIN MAX SDA/SCL TIMING REQUIREMENTS (see Figure 12) fSCL SCL clock frequency 0 100 0 400 kHz tsu(START) START setup time (SCL high before SDA low) 4.7 0.6 ms th(START) START hold time (SCL low after SDA low) 4 0.6 ms tw(SCLL) SCL low-pulse duration 4.7 1.3 ms tw(SCLH) SCL high-pulse duration 4 0.6 ms th(SDA) SDA hold time (SDA valid after SCL low) 0 3.45 0 0.9 ms tsu(SDA) SDA setup time 250 100 ns tr SCL/SDA input rise time 1000 300 ns tf SCL/SDA input fall time 300 300 ns tsu(STOP) STOP setup time 4 0.6 ms tBUS Bus free time between a STOP and START condition 4.7 1.3 ms Copyright © 2007–2010, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): CDCE913 CDCEL913 |
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