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TPIC5421L 데이터시트(PDF) 4 Page - Texas Instruments |
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TPIC5421L 데이터시트(HTML) 4 Page - Texas Instruments |
4 / 16 page TPIC5421L HBRIDGE GATEPROTECTED LOGICLEVEL POWER DMOS ARRAY SLIS027A − OCTOBER 1994 − REVISED OCTOBER 1995 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 resistive-load switching characteristics, TC = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT td(on) Turn-on delay time 25 50 td(off) Turn-off delay time VDD = 25 V, RL = 25 Ω, tr1 = 10 ns, 20 40 ns tr2 Rise time VDD = 25 V, tf1 = 10 ns, RL = 25 Ω, See Figure 2 tr1 = 10 ns, 21 42 ns tf2 Fall time tf1 = 10 ns, See Figure 2 9 18 Qg Total gate charge VDS = 48 V, ID = 0.5 A, VGS = 5 V, 3.9 5 Qgs(th) Threshold gate-to-source charge VDS = 48 V, See Figure 3 ID = 0.5 A, VGS = 5 V, 0.55 0.8 nC Qgd Gate-to-drain charge See Figure 3 2.5 3.6 nC LD Internal drain inductance 5 nH LS Internal source inductance 5 nH Rg Internal gate resistance 0.25 Ω thermal resistance PARAMETER TEST CONDITIONS MIN TYP MAX UNIT R JA Junction-to-ambient thermal resistance DW package See Notes 4 and 6 90 RθJA Junction-to-ambient thermal resistance NE package See Notes 4 and 6 60 RθJB Junction-to-board thermal resistance DW package See Notes 4 and 6 53 °C/W RθJP Junction-to-pin thermal resistance DW package See Notes 5 and 6 30 C/W RθJP Junction-to-pin thermal resistance NE package See Notes 5 and 6 25 NOTES: 4. Package mounted on an FR4 printed-circuit board with no heatsink. 5. Package mounted in intimate contact with infinite heatsink. 6. All outputs with equal power |
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