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CXA1787N 데이터시트(PDF) 8 Page - Sony Corporation |
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CXA1787N 데이터시트(HTML) 8 Page - Sony Corporation |
8 / 13 page – 8 – CXA1787N (a) Data structure of reference counter (First, input the SW bit and input the C bit last.) R0 to RD: Frequency division number of reference counter (Binary value with R0 as LSB) SW: Switching bit of frequency division numbers of 2-modulus pre-scaler block for programmable counter. C: This code decides the latch direction of data; set to High. (b) Data structure of pulse swallow programmable counter (First, input the MA bit and input the C bit last.) M0 to MA: Frequency division number of main counter (Binary value with M0 as LSB) S0 to S6: Frequency division number of swallow counter (Binary value with S0 as LSB) C: This code decides the latch direction of data; set to Low. The frequency division value of programmable counter can be obtained with the following equation; N × M + S N: Frequency division value of 2-modulus pre-scaler (64 or 128) (M > S) M: Main counter value S: Swallow counter value (1) Data input timing SW RD RC RB RA R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 C Input direction MA M9 M8 M7 M6 M5 M4 M3 M2 M1 M0 S6 S5 S4 S3 S2 S1 S0 C Input direction SW Frequency division number 1 64/65-frequency division 0 128/129-frequency division DATA CK LAT (C bit) Data is read at the rising edge of CK. t1 to t5 ≥ 500ns (SW bit or MA bit) t1 t2 t3 t5 t4 |
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