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CXA3086 데이터시트(PDF) 10 Page - Sony Corporation |
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CXA3086 데이터시트(HTML) 10 Page - Sony Corporation |
10 / 30 page – 10 – CXA3086Q Description of Operating Modes The CXA3086Q has two types of operating modes which are selected with Pin 41 (SELECT). 1. DMUX mode (See Application Circuits (1), (2) and (3).) Set the SELECT pin to Vcc for this mode. In this mode, the clock frequency is divided by 2 in the IC, and the data is output after being demultiplexed by this 1/2 frequency divided clock. The 1/2 frequency divided clock, which has adequate setup time and hold time for the output data, is output from the CLKOUT pin. When resetting this 1/2 frequency divided clock, the low level of the RESET signal should be input to the RESETN pin (Pin 10 or 12). The RESET signal requires the setup time (T_rs ≥ 3.5ns) and hold time (T_rh ≥ 0ns) to the clock rising edge because it is synchronized with and taken in the clock. Therefore, set the RESET signal to low for T_rs (min.) + T_rh (min.) = 3.5ns or longer to the clock rising edge. The reset period can be extended by making the low level period of the RESET signal longer because the clock output pin is fixed to low (reset) during the low level period at the clock rising edge. If the reset start timing is regarded as not important, the timing where the RESET signal is set from high to low is not so consequence. However, when the reset is released this timing must become significant because the timing is used to commence the 1/2 frequency divided clock. In this case, the setup time (T_rs) is also necessary. See the timing chart for detail. (This chart shows the example of reset for 2T.) The A/D converter can operate at FC (min.) = 140MSPS in this mode. Table 2. Operating Mode Table SELECT VCC GND DMUX mode Straight mode 140MSPS 100MSPS Demultiplexed output 70Mbps Straight output 100Mbps The input clock is 1/2 frequency divided and output. 70MHz The input clock is inverted and output. 100MHz Operating mode Maximum conversion rate Data output Clock output |
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