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FAN6208 데이터시트(PDF) 9 Page - Fairchild Semiconductor

부품명 FAN6208
상세설명  Secondary-Side Synchronous Rectifier Controller for LLC Topology
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제조업체  FAIRCHILD [Fairchild Semiconductor]
홈페이지  http://www.fairchildsemi.com
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© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN6208 • Rev. 1.0.2
9
VDET
VGATE
2V
VGATE
tDETL (n) - tDEAD
tDETL (n+1)
tSR-ON-DETL
tDETL (n-1) - tDEAD
tDETL (n)
tSR-ON-DETL
Figure 10.SR Gate Timing Diagram
Figure 11.DETL Debounce (Blanking) Time
Gate-Shrink Functions
In normal operation, the turn-off instant is determined by
subtracting a dead time (tDEAD) from the measured SR
conduction duration of the previous switching cycle, as
shown in Figure 10. This allows proper driving timing for
SR MOSFETS when the converter is in steady state and
the switching frequency does not change much.
However, this control method may cause shoot-through
of SR MOSFETs when the switching frequency
increases fast and switching transition of the primary-
side MOSFETs takes place before the turn-off
command of SR is given. To prevent the shoot-through,
FAN6208 has gate-shrink functions. Gate shrink occurs
under three conditions:
(a) When insufficient dead time is detected in the
previous switching cycle. When the DETL goes
HIGH within 125ns of detection window after SR
gate is turned off, the SR gate drive signal in the
next switching cycle is reduced by tSHRINK-DT (about
1.25µs) to increase the dead time, as shown in
Figure 12.
VDET
VGATE
2V
VGATE
tDETL_LOW (n) – tDEAD– tSHRINK
tDETL_LOW (n+1)
125ns
tDETL_LOW (n-1) - tDEAD
tDETL_LOW (n)
Detection window
Shrink
Figure 12.Gate Shrink by Minimum Dead Time
Detection Window
(b) When the feedback information changes fast.
FAN6208 monitors the current through the opto-
coupler diode by measuring the voltage across the
resistor in series with the opto-coupler diode, as
depicted in Figure 13. If the feedback current
through the opto-coupler diode increases by more
than 20% of the feedback current of the previous
switching cycle, the SR gate signal is shrunk by
tSHRINK-FD (about 1.4µs) for tD-SHRINK-FD (about 90µs),
as shown in Figure 14.
Figure 13.Typical Application Circuit


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