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FAN53600 데이터시트(PDF) 11 Page - Fairchild Semiconductor |
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FAN53600 데이터시트(HTML) 11 Page - Fairchild Semiconductor |
11 / 16 page © 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN53600 / FAN53610 • Rev. 1.0.0 11 Operation Description The FAN53600/10 is a 3 MHz, step-down switching voltage regulator, available in 600 mA or 1 A options, that delivers a fixed output from an input voltage supply of 2.3 V to 5.5 V. Using a proprietary architecture with synchronous rectification, the FAN53600/10 is capable of delivering a peak efficiency of 92%, while maintaining efficiency over 80% at load currents as low as 1 mA. The regulator operates at a nominal fixed frequency of 3 MHz, which reduces the value of the external components to as low as 1 µH for the output inductor and 4.7 µF for the output capacitor. In addition, the PWM modulator can be synchronized to an external frequency source. Control Scheme The FAN53600/10 uses a proprietary, non-linear, fixed- frequency PWM modulator to deliver a fast load transient response, while maintaining a constant switching frequency over a wide range of operating conditions. The regulator performance is independent of the output capacitor ESR, allowing the use of ceramic output capacitors. Although this type of operation normally results in a switching frequency that varies with input voltage and load current, an internal frequency loop holds the switching frequency constant over a large range of input voltages and load currents. For very light loads, the FAN53600/10 operates in Discontinuous Current (DCM), single-pulse, PFM Mode; which produces low output ripple compared with other PFM architectures. Transition between PWM and PFM is seamless, with a glitch of less than 18 mV at VOUT during the transition between DCM and CCM modes. Combined with exceptional transient response characteristics, the very low quiescent current of the controller (26 µA) maintains high efficiency, even at very light loads, while preserving fast transient response for applications requiring tight output regulation. 100% Duty Cycle Operation When VIN approaches VOUT, the regulator increases its duty cycle until 100% duty cycle is reached. As the duty cycle approaches 100%, the switching frequency declines due to the minimum off-time (tOFF(MIN)) of about 50 ns imposed by the control circuit. When 100% duty cycle is reached, VOUT follows VIN with a drop-out voltage (VDROPOUT) determined by the total resistance between VIN and VOUT as calculated by: ( ) L ) ON ( DS LOAD DROPOUT DCR R PMOS I V + • = (1) Enable and Soft-Start When EN is LOW, all circuits are off and the IC draws ~50 nA of current. When EN is HIGH and VIN is above its UVLO threshold, the regulator begins a soft-start cycle. The output ramp during soft-start is a fixed slew rate of 50 mV/ μs from 0 to 1 VOUT, then 12.5 mV/ μs until the output reaches its setpoint. Regardless of the state of the MODE pin, PFM Mode is enabled to prevent current from being discharged from COUT if soft-start begins when COUT is charged. All voltage options can be ordered with a feature that actively discharges FB to ground through a 230 Ω path when EN is LOW. Raising EN above its threshold voltage activates the part and starts the soft-start cycle. During soft-start, the internal reference is ramped using an exponential RC shape to prevent overshoot of the output voltage. Current limiting minimizes inrush during soft-start. The IC may fail to start if heavy load is applied during startup and/or if excessive COUT is used. This is due to the current- limit fault response, which protects the IC in the event of an over-current condition present during soft-start. The current required to charge COUT during soft-start, commonly referred to as “displacement current,” is given as: dt dV C I OUT DISP • = (2) where the dt dV term refers to the soft-start slew rate above. To prevent shutdown during soft-start, the following condition must be met: ) (DC MAX LOAD DISP I I I < + (3) where IMAX(DC) is the maximum load current the IC is guaranteed to support. Startup into Large COUT Multiple soft-start cycles are required for no-load startup if COUT is greater than 15 μF. Large COUT requires light initial load to ensure the FAN53600/10 starts appropriately. The IC shuts down for 1.3 ms when IDISP exceeds ILIMIT for more than 210 μs of current limit. The IC then begins a new soft- start cycle. Since COUT retains its charge when the IC is off, the IC reaches regulation after multiple soft-start attempts. MODE Pin Logic 1 on this pin forces the IC to stay in PWM Mode. Logic 0 allows the IC to automatically switch to PFM during light loads. If the MODE pin is toggled, with a frequency between 1.3 MHz and 1.7 MHz, the converter synchronizes its switching frequency to two times the frequency on the MODE pin (fMODE). The MODE pin is internally buffered with a Schmitt trigger, which allows the MODE pin to be driven with slow rise and fall times. An asymmetric duty cycle for frequency synchronization is also permitted as long as the minimum time below VIL(MAX) or above VIH(MAX) is 100 ns. |
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