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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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FM25L04B-GTR 데이터시트(PDF) 6 Page - Cypress Semiconductor |
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FM25L04B-GTR 데이터시트(HTML) 6 Page - Cypress Semiconductor |
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6 / 14 page  FM25L04B - Automotive Temp. Document Number: 001-86152 Rev. *A Page 6 of 14 RDSR - Read Status Register The RDSR command allows the bus master to verify the contents of the Status Register. Reading status provides information about the current state of the write protection features. Following the RDSR op- code, the FM25L04B will return one byte with the contents of the Status Register. The Status Register is described in detail in a later section. WRSR – Write Status Register The WRSR command allows the user to select certain write protection features by writing a byte to the Status Register. Prior to issuing a WRSR command, the /WP pin must be high or inactive. Prior to sending the WRSR command, the user must send a WREN command to enable writes. Note that executing a WRSR command is a write operation and therefore clears the Write Enable Latch. Figure 7. RDSR Bus Configuration Figure 8. WRSR Bus Configuration (WREN not shown) Status Register & Write Protection The write protection features of the FM25L04B are multi-tiered. Taking the /WP pin to a logic low state is the hardware write protect function. All write operations are blocked when /WP is low. To write the memory with /WP high, a WREN op-code must first be issued. Assuming that writes are enabled using WREN and by /WP, writes to memory are controlled by the Status Register. As described above, writes to the status register are performed using the WRSR command and subject to the /WP pin. The Status Register is organized as follows. Table 2. Status Register Bit 7 6 5 4 3 2 1 0 Name 0 0 0 0 BP1 BP0 WEL 0 Bits 0 and 7-4 are fixed at 0 and cannot be modified. Note that bit 0 (“Ready” in EEPROMs) is unnecessary as the F-RAM writes in real-time and is never busy. The BP1 and BP0 control write protection features. They are nonvolatile (shaded yellow). The WEL flag indicates the state of the Write Enable Latch. Attempting to directly write the WEL bit in the Status Register has no effect on its state. This bit is internally set and cleared via the WREN and WRDI commands, respectively. BP1 and BP0 are memory block write protection bits. They specify portions of memory that are write-protected as shown in the following table. Table 3. Block Memory Write Protection BP1 BP0 Protected Address Range 0 0 None 0 1 180h to 1FFh (upper ¼) 1 0 100h to 1FFh (upper ½) 1 1 000h to 1FFh (all) The BP1 and BP0 bits allow software to selectively write-protect the array. These settings are only used when the /WP pin is inactive and the WREN command has been issued. The following table summarizes the write protection conditions. |
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