전자부품 데이터시트 검색엔진 |
|
LC08101CT 데이터시트(PDF) 11 Page - Sanyo Semicon Device |
|
LC08101CT 데이터시트(HTML) 11 Page - Sanyo Semicon Device |
11 / 20 page LC08101CT No.A2010-11/20 Serial Mode Settings 0 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 D0 to D6: DRVPULSE [6 : 0] Operation count setting register. Specify a number from 0 to 127. The number of cyclic operations determined by <DRVPLUSE setting> × <STP setting> are performed. Additional data can be input and data is added up to the equivalent of total of 512 pulses. However, if the ENIN register is set to 0, the DRVPULSE input is not accepted because the DRVPULSE counter is in the reset state. Since the output operation is carried out at the time the DRVPULSE input is recognized, the generation of the OUT signal is started at the time an ACK signal is generated after the execution of the instruction at address 00H according to the value of the waveform setup register established at that time. D7 M/I Operation direction switching 0 ∞ *Default Infinity distance direction 1 macro Macro direction Operation direction switching register The operation count setting register is reset when the register is switched. To stop the operation of the unit, switch the M/I register and set DRVPULSE to 0 for input. 1 0 0 0 0 0 0 0 1 0 0 D5 D4 D3 D2 D1 D0 D0: The register who selects whether you output brakes pulse after the movement end by the DRVPULSE input automatically. D0 BRON Initialization to be performed/not to be performed setting 0 No brake *Default 1 On brake D1, D2: The register who sets frequency of the oscillatory frequency when you operate an internal oscillator circuit. D2 D1 INCLK Number of initialization sequence swing back 0 0 Oscillator stop *Default 0 1 1.02MHz 1 0 1MHz 1 1 0.98MHz D3, D4: Register (when I use an internal oscillation invalidity) who sets the ratio to do a share lap when I count it in a clock pulse input into CLK pin or the IC inside as basic time. D4 D3 CKSEL Input clock division ratio switching 0 0 1/4 *Default 1/4 0 1 1/2 1/2 1 0 1 1 (no frequency division) 1 1 1 1 (no frequency division) D5 : ENIN ENIN register is a register setting start, the stop of the IC. Only as for the state of ENIN=1, the output of the IC operates. It becomes a wait mode at the time of ENIN=0. 2 0 0 0 0 0 0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 RST7 to RST0 : Specifies the number of clocks per period (0 to 255). Default = 0 3 0 0 0 0 0 0 1 1 D7 D6 D5 D4 D3 D2 D1 D0 GTAS7 to GTAS0 : Sets the GATE_A pulse set value (0 to 255). Default = 0 |
유사한 부품 번호 - LC08101CT |
|
유사한 설명 - LC08101CT |
|
|
링크 URL |
개인정보취급방침 |
ALLDATASHEET.CO.KR |
ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |