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AD1674BD 데이터시트(PDF) 11 Page - Analog Devices |
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AD1674BD 데이터시트(HTML) 11 Page - Analog Devices |
11 / 12 page AD1674 REV. C –11– 100k AD1674 R1 100k –15V +15V R2 100 Ω 100 Ω ANALOG INPUTS 0 TO +20V 0 TO +10V 2 12/8 3 CS 4 A 0 5 R/C 6 CE 10 REF IN 8 REF OUT 12 BIP OFF 13 10V IN 14 20V IN 9 ANA COM STS 28 HIGH BITS 24-27 MIDDLE BITS 20-23 LOW BITS 16-19 +5V 1 +15V 7 –15V 11 DIG COM 15 Figure 11. Unipolar Input Connections with Gain and Offset Trims The full-scale trim is done by applying a signal 1 1/2 LSB below the nominal full scale (9.9963 V for a 10 V range) and adjusting R2 until the last transition is located (1111 1111 1110 to 1111 1111 1111). If full-scale adjustment is not required, R2 should be replaced with a fixed 50 Ω ±1% metal film resistor. If REF OUT is connected directly to REF IN, the additional full-scale error will be approximately 1%. BIPOLAR RANGE INPUTS The connections for the bipolar-input mode are shown in Figure 12. Either or both of the trimming potentiometers can be replaced with 50 Ω ± 1% fixed resistors if the specified AD1674 accuracy limits are sufficient for the application. If the pins are shorted together, the additional offset and gain errors will be approximately 1%. To trim bipolar offset to its nominal value, apply a signal 1/2 LSB below midrange (–1.22 mV for a ±5 V range) and adjust R1 until the major carry transition is located (0111 1111 1111 to 1000 0000 0000). To trim the full-scale error, apply a signal 1 1/2 LSB below full scale (+4.9963 V for a ±5 V range) and adjust R2 to give the last positive transition (1111 1111 1110 to 1111 1111 1111). These trims are interactive so several itera- tions may be necessary for convergence. A single-pass calibration can be done by substituting a negative full-scale trim for the bipolar offset trim (error at midscale), using the same circuit. First, apply a signal 1/2 LSB above minus full scale (–4.9988 V for a ±5 V range) and adjust R1 until the minus full-scale transition is located (0000 0000 0001 to 0000 0000 0000). Then perform the gain error trim as outlined above. R1 100 Ω ±10V ±5V AD1674 R2 100 Ω ANALOG INPUTS 2 12/8 3 CS 4 A 0 5 R/C 6 CE 10 REF IN 8 REF OUT 12 BIP OFF 13 10V IN 14 20V IN 9 ANA COM STS 28 HIGH BITS 24-27 MIDDLE BITS 20-23 LOW BITS 16-19 +5V 1 +15V 7 –15V 11 DIG COM 15 Figure 12. Bipolar Input Connections with Gain and Offset Trims REFERENCE DECOUPLING It is recommended that a 10 µF tantalum capacitor be con- nected between REF IN (Pin 10) and ground. This has the effect of improving the S/(N+D) ratio through filtering possible broad-band noise contributions from the voltage reference. BOARD LAYOUT Designing with high resolution data converters requires careful attention to board layout. Trace impedance is a significant issue. At the 12-bit level, a 5 mA current through a 0.5 Ω trace will develop a voltage drop of 2.5 mV, which is 1 LSB for a 10 V full-scale range. In addition to ground drops, inductive and ca- pacitive coupling need to be considered, especially when high accuracy analog signals share the same board with digital sig- nals. Finally, power supplies should be decoupled in order to filter out ac noise. The AD1674 has a wide bandwidth sampling front end. This means that the AD1674 will “see” high frequency noise at the input, which nonsampling (or limited-bandwidth sampling) ADCs would ignore. Therefore, it’s important to make an effort to eliminate such high frequency noise through decoupling or by using an anti-aliasing filter at the analog input of the AD1674. Analog and digital signals should not share a common path. Each signal should have an appropriate analog or digital return routed close to it. Using this approach, signal loops enclose a small area, minimizing the inductive coupling of noise. Wide PC tracks, large gauge wire, and ground planes are highly recom- mended to provide low impedance signal paths. Separate analog and digital ground planes are also desirable, with a single inter- connection point to minimize ground loops. Analog signals should be routed as far as possible from digital signals and should cross them (if necessary) only at right angles. The AD1674 incorporates several features to help the user’s lay- out. Analog pins are adjacent to help isolate analog from digital signals. Ground currents have been minimized by careful circuit architecture. Current through AGND is 2.2 mA, with little code-dependent variation. The current through DGND is domi- nated by the return current for DB11–DB0. SUPPLY DECOUPLING The AD1674 power supplies should be well filtered, well regu- lated, and free from high frequency noise. Switching power sup- plies are not recommended due to their tendency to generate spikes which can induce noise in the analog system. Decoupling capacitors should be used in very close layout prox- imity between all power supply pins and ground. A 10 µF tanta- lum capacitor in parallel with a 0.1 µF disc ceramic capacitor provides adequate decoupling over a wide range of frequencies. An effort should be made to minimize the trace length between the capacitor leads and the respective converter power supply and common pins. The circuit layout should attempt to locate the AD1674, associated analog input circuitry, and interconnec- tions as far as possible from logic circuitry. A solid analog ground plane around the AD1674 will isolate large switching ground currents. For these reasons, the use of wire-wrap circuit construction is not recommended; careful printed-circuit con- struction is preferred. |
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