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AD1959YRS 데이터시트(PDF) 6 Page - Analog Devices |
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AD1959YRS 데이터시트(HTML) 6 Page - Analog Devices |
6 / 8 page REV. 0 AD1959 –6– FUNCTIONAL DESCRIPTION DAC The AD1959 has two DAC channels arranged as a stereo pair with single-ended analog outputs. Each channel has its own independently programmable attenuator, adjustable in 16384 linear steps. Digital inputs are supplied through a serial data input pin, SDATA, a frame clock, LRCLK and a bit clock, BLCK. Each analog output pin sits at a dc level of VREF, and swings ± 1.585 V for a 0 dB digital input signal. A single op amp third-order external low-pass filter is recommended to remove high-frequency noise present on the output pins. The output phase can be changed in an SPI control register to accommo- date inverting and noninverting filters. Note that the use of op amps with low slew rate or low bandwidth may cause high fre- quency noise and tones to fold down into the audio band; care should be exercised in selecting these components. The FILTD and FILTR pins should be bypassed by external capacitors to ground. The FILTD pin is used to reduce the noise of the internal DAC bias circuitry, thereby reducing the DAC output noise. The voltage at the VREF pin, FILTR (~2.39 V) can be used to bias external op amps used to filter the output signals. The DAC master clock frequency is 256 fS for the 32 kHz–48 kHz range. For the 96 kHz range this is 128 fS. It is supplied inter- nally from the PLL clock system when MCLK mode is set to Output in the PLL Control Register. When the MCLK mode is changed to Input, it must be supplied from an external source connected to MCLK. The output from the 27 MHz PLL clock is disabled in this case. PLL Clock System The PLL clock system operates from a 27 MHz master clock supplied by the on-board crystal oscillator or an external source connected to XIN. With the MCLK mode set to Output, the 27 MHz clock is buffered out to the MCLK pin. When set to Input, the MCLK is the 256 fS master clock input for the DAC. SCLK0 produces a 33.8688 MHz output, SCLK1 is intended to be used as a master audio clock and will be a multiple of the sample rate set in the PLL control register. It can be set to 256 fS or 384 fS using Bit 5 and to 512 fS or 768 fS, with Bit 4. SCLK2 can be set to a constant 22.5792 MHz (512 × 44.1 kHz) or 512 fS by Bit 3 of the PLL Control Register. Please note that SCLK2 is intended to operate a DSP and does not meet the jitter specifications stated under Analog Performance. All the generated clocks can be set to 1/2 their nominal rate by setting REF_Div2, Bit 8 in the PLL Control Register. Reset RESET will set the control registers to their default settings. The chip should be reset on power-up. After reset is deasserted, the part will come out of reset on the next rising LRCLK. Serial Control Port The AD1959 has an SPI-compatible control port to permit programming the internal control registers for the PLL and DAC. The DAC output levels may be independently programmed by means of an internal digital attenuator adjustable in 16384 linear steps. The SPI control port is a 3-wire serial control port. The format is similar to the Motorola SPI format except the input data word is 16 bits wide. Max serial bit clock frequency is 8 MHz and may be completely asynchronous to the PLL system or the DAC. Figure 1 shows the format of the SPI signal. Note that the CCLK can be gated or continuous, CLATCH should be low during the 16 active clocks. CLATCH CCLK CDATA D0 D15 D14 Figure 1. Format of SPI Signal |
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