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AD2S105 데이터시트(PDF) 6 Page - Analog Devices |
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AD2S105 데이터시트(HTML) 6 Page - Analog Devices |
6 / 12 page AD2S105 REV. 0 –6– ANALOG SIGNAL INPUT AND OUTPUT CONNECTIONS Input Analog Signals All analog signal inputs to AD2S105 are voltages. There are two different voltage levels of three-phase (0 °, 120°, 240°) signal in- puts. One is the nominal level, which is ±2.8 V dc or 2 V rms and the corresponding input pins are PH/IP1 (Pin 17), PH/IP2 (Pin 15), PH/IP3 (Pin 13) and PH/IP4 (Pin 11). The high level inputs can accommodate voltages from nominal up to a maximum of ±V DD/VSS. The corresponding input pins are PH/IPH1 (Pin 16), PH/IPH2 (Pin 14) and PH/IPH3 (Pin 12). The homopolar output can only be used in the three-phase connection mode. The converter can accept both two-phase format and three- phase format input signals. For the two-phase format input, the two inputs must be orthogonal to each other. For the three- phase format input, there is the choice of using all three inputs or using two of the three inputs. In the latter case, the third in- put signal will be generated internally by using the information of other two inputs. The high level input mode, however, can only be selected with three-phase/three-input format. All these different conversion modes, including nominal/high input level and two/three-phase input format can be selected using two se- lect pins (Pin 23, Pin 24). The functions are summarized in Table I. Table I. Conversion Mode Selection CONV1 CONV2 Mode Description (Pin 23) (Pin 24) MODE1 2-Phase Orthogonal with 2 Inputs NC DGND Nominal Input Level MODE2 3-Phase (0 °, 120°, 240°) with 3 Inputs DGND VDD Nominal/High Input Level* MODE3 3-Phase (0 °, 120°, 240°) with 2 Inputs V DD VDD Nominal Input Level *The high level input mode can only be selected with MODE2. MODE1: 2-Phase/2 Inputs with Nominal Input Level In this mode, PH/IP1 and PH/IP4 are the inputs and the Pins 12 through 16 must be left unconnected. MODE2: 3-Phase/3 Inputs with Nominal/High Input Level In this mode, either nominal or high level inputs can be used. For nominal level input operation, PH/IP1, PH/IP2 and PH/IP3 are the inputs, and there should be no connections to PH/IPH1, PH/IPH2 and PH/IPH3; similarly, for high level input opera- tion, the PH/IPH1, PH/IPH2 and PH/IPH3 are the inputs, and there should be no connections to PH/IP1, PH/IP2 and PH/IP3. In both cases, the PH/IP4 should be left unconnected. For high level signal input operation, select MODE2 only. MODE3: 3-Phase/2 Inputs with Nominal Input Level In this mode, PH/IP2 and PH/IP3 are the inputs and the third signal will be generated internally by using the information of other two inputs. It is recommended that PH/IP1, PH/IPH1, PH/IPH2, PH/IP4 and PH/IPH3 should be left unconnected. CONVERTER OPERATION The architecture of the AD2S105 is illustrated in Figure 3. The AD2S105 is configured in the forward transformation which ro- tates the stator coordinates to the rotor reference frame. Vector Rotation Position data, , is loaded into the input latch on the positive edge of the strobe pulse. (For detail on the timing, please refer to the “timing diagram.”) The negative edge of the strobe signi- fies that conversion has commenced. A busy pulse is subse- quently produced as data is passed from the input latches to the Sin and Cos multipliers. During the loading of the multiplier, the busy pulse remains high preventing further updates of in both the Sin and Cos registers. The negative edge of the busy pulse signifies that the multipliers are set up and the orthogonal analog inputs are then multiplied real time. The resultant two outputs are accessed via the PH/OP1 (Pin 7) and PH/OP4 (Pin 6). For other configurations, please refer to “Transformation Configuration.” CONNECTING THE CONVERTER Power Supply Connection The power supply voltages connected to VDD and VSS pins should be +5 V dc and –5 V dc and must not be reversed. Pin 4 (VDD) and Pin 41 (VDD) should both be connected to +5 V; similarly, Pin 5 (VSS) and Pin 19 (VSS) should both be con- nected to –5 V dc. It is recommended that decoupling capacitors, 100 nF (ceramic) and 10 µF (tantalum) or other high quality capacitors, are con- nected in parallel between the power line VDD, VSS and AGND adjacent to the converter. Separate decoupling capacitors should be used for each converter. The connections are shown in Fig- ure 4. AD2S105 TOP VIEW 1 23 12 34 AGND 100nF 100nF 10 µF 10 µF + + +5V GND –5V Figure 4. AD2S105 Power Supply Connection |
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