AD5204/AD5206

–10–

REV. 0

RDAC 1

RDAC 2

RDAC 4/6

AD5204/AD5206

SDI

CLK

CS

ADDR

DECODE

SERIAL

REGISTER

Figure 18. Equivalent Input Control Logic

The target RDAC latch is loaded with the last eight bits of the

serial data word completing one DAC update. Four separate 8-

bit data words must be clocked in to change all four VR settings.

SERIAL

REGISTER

SDI

CK

RS

D

Q

SHDN

CS

CLK

PR

SDO

GND

Figure 19. Detail SDO Output Schematic of the AD5204

All digital pins are protected with a series input resistor and

parallel Zener ESD structure shown in Figure 20. Applies to

digital pins

CS, SDI, SDO, PR, SHDN, CLK

340k

LOGIC

Figure 20. ESD Protection of Digital Pins

A, B, W

Figure 21. ESD Protection of Resistor Terminals

V+

DUT

A

B

W

1LSB = V+/256

Figure 22. Potentiometer Divider Nonlinearity Error Test

Circuit (INL, DNL)

NO CONNECT

DUT

A

B

W

Figure 23. Resistor Position Nonlinearity Error (Rheostat

Operation; R-INL, R-DNL)

DUT

A

B

W

V+

V+

Figure 24. Wiper Resistance Test Circuit

PSRR (dB) = 20 LOG

PSS (%/%) = –––––––

~

V+

A

B

W

Figure 25. Power Supply Sensitivity Test Circuit (PSS,

PSRR)

AB

OP279

+5V

DUT

W

OFFSET

GND

+

OFFSET BIAS

Figure 26. Inverting Programmable Gain Test Circuit

AB

OP279

+5V

DUT

W

OFFSET

GND

OFFSET BIAS

Figure 27. Noninverting Programmable Gain Test Circuit

+15V

–15V

A

B

2.5V

OP42

DUT

W

OFFSET

GND

+

Figure 28. Gain vs. Frequency Test Circuit

0.1V

0.1V

DUT

B

W

+

Figure 29. Incremental ON Resistance Test Circuit