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AD608 데이터시트(PDF) 8 Page - Analog Devices |
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AD608 데이터시트(HTML) 8 Page - Analog Devices |
8 / 12 page REV. B –8– AD608 IF Filter Terminations The AD608 was designed to drive a parallel-terminated 10.7 MHz bandpass filter with a 330 Ω impedance. With a 330 Ω parallel- terminated filter, pin MXOP sees a 165 Ω termination and the gain is nominally 24 dB. Other filter impedances and gains can be accommodated by either accepting an increase or decrease in gain in proportion to the filter impedance or by keeping the im- pedance seen by MXOP a nominal 165 Ω (by using resistive di- viders or matching networks). Figure 21 shows a simple resistive voltage divider for matching an assortment of filter impedances, and Table II lists component values. The Logarithmic IF Amplifier The logarithmic IF amplifier consists of five amplifier stages of 16 dB gain each, plus a final limiter. The IF bandwidth is 30 MHz (–1 dB) and the limiting gain is 110 dB. The phase skew is ± 3° from –75 dBm to +5 dBm (approximately 111 µV p-p to 1.1 V p-p). The limiter output impedance is 200 Ω and the limiter’s output drive is ± 200 mV (400 mV p-p) into a 5 k Ω load. In the absence of an input signal, the limiter’s output will limit on noise fluctuations, which produces an output that continues to swing 400 mV p-p but with random zero crossings. Offset Feedback Loop Because the logarithmic amplifier is dc coupled and has more than 110 dB of gain from the input to the limiter output, a dc offset at its input of even a few µV would cause the output to saturate. Thus, the AD608 uses a low frequency feedback loop to null out the input offset. Referring to Figure 21, the loop consists of a current source driven by the limiter, which sends 50 µA current pulses to pin FDBK. The pulses are low pass filtered by a π-network consisting of C1, R4, and C5. The smoothed dc voltage that results is subtracted from the input to the IF amplifier at pin IFLO. Because this is a high gain ampli- fier with a feedback loop, care should be taken in layout and component values to prevent oscillation. Recommended values for the common IFs of 450 kHz, 455 kHz, 6.5 MHz, and 10.7 MHz are listed in Table II. 24dB MIXER GAIN 110dB LIMITER GAIN 90dB RSSI BIAS MXOP MIXER BPF DRIVER VMID LO PREAMP AD608 RFHI RFLO IFHI IFLO LMOP VPS2 RSSI FDBK COM3 FINAL LIMITER 100nF C5 R1 ±50µA BANDPASS FILTER MID-SUPPLY IF BIAS 6 5 7 8 10 9 13 14 12 15 11 1 2 3 4 16 PRUP VPS1 COM1 COM2 LOHI 12dB NOMINAL INSERTION LOSS (ASSUMES 6dB IN FILTER) 5-STAGE IF AMPLIFIER (16dB PER STAGE) 7 FULL-WAVE RECTIFIER CELLS ≈ ≈ R4 C1 +5V C1 1 µF LO INPUT –16dBm C2 100pF CMOS LOGIC INPUT R2 R3 2MHz LPF 47k Ω Figure 21. Applications Diagram for Common IFs and Filter Impedances Table II. AD608 Filter Termination and Offset-Null Feedback Loop Resistor and Capacitor Values for Common IFs Filter Filter Termination Resistor Offset Null IF Impedance Values 1 for 24 dB of Mixer Gain Feedback Loop Values R1 R2 R3 R4 C1 C5 450 kHz 2 1500 Ω 174 Ω 1330 Ω 1500 Ω 1000 Ω 200 nF 100 nF 455 kHz 1500 Ω 174 Ω 1330 Ω 1500 Ω 1000 Ω 200 nF 100 nF 6.5 MHz 1000 Ω 178 Ω 825 Ω 1000 Ω 100 Ω 18 nF 10 nF 10.7 MHz 330 Ω 330 Ω 0 Ω 330 Ω 100 Ω 18 nF 10 nF NOTES 1Resistor values were calculated so that R1 + R2 = Z FILTER and R1 (R2+ZFILTER) = 165 Ω. 2Operation at IFs of 450 kHz and 455 kHz requires an external low pass filter with at least one pole at a cutoff frequency of 90 kHz (a decade below the ripple at 900 kHz). |
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