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AD6402 데이터시트(PDF) 2 Page - Analog Devices |
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AD6402 데이터시트(HTML) 2 Page - Analog Devices |
2 / 8 page –2– REV. 0 AD6402–SPECIFICATIONS AD6402ARS Parameter Conditions Min Typ Max Units IF BANDPASS FILTER Center Frequency Rejection REFIN = 13.824 MHz, REFSEL <0.2 V CC 20.736 MHz F O ± 3.0 MHz 7 dBc F O ± 4.7 MHz 13 dBc F O ± 6.0 MHz 16 dBc Stop Band Rejection 30 dBc RECEIVER Sensitivity FM Modulated 576 kHz, FM Deviation 288 kHz –80 dBm BT = 0.5, Demod Output SNR = 10 dB, R S = 150 Ω RSSI Low V OUT = 0.2 V, RS = 150 Ω –85 dBm High V OUT = 1.8 V, RS = 150 Ω –5 dBm Slope See Figure 4 20 mV/dB Output Impedance 4k Ω DEMODULATOR Gain At Data Filter Output 1.2 1.55 V/MHz Offset Referred to SLREF –200 +200 mV Lock Time From SLEEP Mode 200 µs From RXLOCK Mode 20 µs DATA FILTER OP AMP Gain 2 Slew Rate C LOAD = 30 pF 8 V/ µs Gain Bandwidth C LOAD = 30 pF 15 MHz Output Swing Low 0.2 V Output Swing High V CC–0.2 V Output Impedance 50 Ω IF VCO Frequency Note 1 131 MHz SSB Phase Noise @ 5 MHz Offset –139 dBc/Hz Output Power Differential RLOAD = 300 Ω –12 dBm 2nd Harmonic –22 dB 3rd Harmonic –24 dB TRANSMIT FILTER OP AMP Open Loop Gain 75 dB Unity Gain Bandwidth CLOAD = 30 pF 12 MHz Output Slew Rate CLOAD = 30 pF 5 V/ µs Minimum Input Voltage 1V Maximum Input Voltage VCC–0.2 V Minimum Output Voltage 0.2 V Maximum Output Voltage VCC–0.2 V POWER CONTROL Logical High Threshold 0.8 × V CC V Logical Low Threshold 0.2 × V CC V Turn-On Response Time VCC Steady State 0.5 µs VOLTAGE REFERENCE SLREF 1.3 1.5 V SUPPLY REGULATOR Output Voltage For Battery Voltages from 3.1 V to 4.5 V 2.75 2.95 V Turn-On Time 1 mV Settling, CLOAD = 100 nF 200 µs Line Regulation 200 mV Battery Step; 5 mV Settling 1 µs Load Regulation 10 µA to 30 mA Step; 5 mV Settling 200 µs POWER SUPPLY All VCC at 2.85 V Supply Current RXLOCKP 30 mA RXLOCK 17 mA RXDEMOD 26 mA TRANSMIT 6 mA STANDBY 300 µA SLEEP 10 µA NOTES 1Using test tank circuit as shown. Specifications subject to change without notice. |
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