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AD6640PCB 데이터시트(PDF) 2 Page - Analog Devices

부품명 AD6640PCB
상세설명  12-Bit, 65 MSPS IF Sampling A/D Converter
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

AD6640PCB 데이터시트(HTML) 2 Page - Analog Devices

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DC SPECIFICATIONS
Test
AD6640AST
Parameter
Temp
Level
Min
Typ
Max
Units
RESOLUTION
12
Bits
ACCURACY
No Missing Codes
+25
°C
I
GUARANTEED
Offset Error
Full
VI
–10
3.5
+10
mV
Gain Error
Full
VI
–10
4.0
+10
% FS
Differential Nonlinearity (DNL)
1
+25
°C
I
–1.0
±0.5
+1.5
LSB
Integral Nonlinearity (INL)
1
Full
V
±1.25
LSB
TEMPERATURE DRIFT
Offset Error
Full
V
50
ppm/
°C
Gain Error
Full
V
100
ppm/
°C
POWER SUPPLY REJECTION (PSRR)
Full
V
±0.5
mV/V
REFERENCE OUT (VREF)
2
Full
V
2.4
V
ANALOG INPUTS (AIN,
AIN)3
Analog Input Common-Mode Range
4
Full
V
VREF ± 0.05
V
Differential Input Voltage Range
Full
V
2.0
V p-p
Differential Input Resistance
Full
IV
0.7
0.9
1.1
k
Differential Input Capacitance
+25
°C
V
1.5
pF
POWER SUPPLY
Supply Voltage
AVCC
Full
VI
4.75
5.0
5.25
V
DVCC
Full
VI
3.0
3.3
5.25
V
Supply Current
IAVCC (AVCC = 5.0 V)
Full
VI
135
160
mA
IDVCC (DVCC = 3.3 V)
Full
VI
10
20
mA
POWER CONSUMPTION
Full
VI
710
865
mW
NOTES
1 ENCODE = 20 MSPS
2 If V
REF is used to provide a dc offset to other circuits, it should first be buffered.
3The AD6640 is designed to be driven differentially. Both AIN and
AIN should be driven at levels V
REF ± 0.5 volts. The input signals should be 180 degrees out of phase to
produce a 2 V p-p differential input signal. See Driving the Analog Inputs section for more details.
4 Analog input common-mode range specifies the offset range the analog inputs can tolerate in dc-coupled applications (see Figure 35 for more detail).
Specifications subject to change without notice
.
DIGITAL SPECIFICATIONS
Test
AD6640AST
Parameter
Temp
Level
Min
Typ
Max
Units
LOGIC INPUTS (ENC,
ENC)1
Encode Input Common-Mode Range
2
Full
IV
0.2
2.2
V
Differential Input Voltage
Full
IV
0.4
V p-p
Single-Ended Encode
10
V p-p
Logic Compatibility3
TTL/CMOS
Logic “1” Voltage
Full
VI
2.0
5.0
V
Logic “0” Voltage
Full
VI
0
0.8
V
Logic “1” Current (VINH = 5 V)
Full
VI
500
650
800
µA
Logic “0” Current (VINL = 0 V)
Full
VI
–400
–320
–200
µA
Input Capacitance
+25
°C
V
2.5
pF
LOGIC OUTPUTS (
D11–D0)4
Logic Compatibility
CMOS
Logic “1” Voltage (DVCC = +3.3 V)
Full
VI
2.8
DVCC – 0.2
V
Logic “0” Voltage (DVCC = +3.3 V)
Full
VI
0.2
0.5
V
Logic “1” Voltage (DVCC = +5.0 V)
Full
IV
4.5
DVCC – 0.3
V
Logic “0” Voltage (DVCC = +5.0 V)
Full
IV
0.35
0.5
V
Output Coding
Twos Complement
NOTES
1Best dynamic performance is obtained by driving ENC and
ENC differentially. See Encoding the AD6640 section for more details. Performance versus ENC/ENC power is
shown in Figure 18 under Typical Performance Characteristics.
2For dc-coupled applications, Encode Input Common-Mode Range specifies the common-mode range the encode inputs can tolerate when driven differentially by minimum
differential input voltage of 0.4 V p-p. For differential input voltage swings greater than 0.4 V p-p, the common-mode range will change. The minimum value insures that the
input voltage on either encode pin does not go below 0 V. The maximum value insures that the input voltage on either encode pin does not go below 2.0 V or above AV CC (e.g.,
for a differential input swing of 0.8 V, the min and max common-mode specs become 0.4 V and 2.4 V respectively).
3ENC or
ENC may be driven alone if desired, but performance will likely be degraded. Logic Compatibility specifications are provided to show that TTL or CMOS clock sources
will work. When driving only one encode input, bypass the complementary input to GND with 0.01
µF.
4Digital output load is one LCX gate.
Specifications subject to change without notice.
REV. 0
(AVCC = +5 V, DVCC = +3.3 V; TMIN = –40 C, TMAX = +85 C)
–2–
AD6640–SPECIFICATIONS
(AVCC = +5 V, DVCC = +3.3 V; TMIN = –40 C, TMAX = +85 C)


유사한 부품 번호 - AD6640PCB

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