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AD679JN 데이터시트(PDF) 6 Page - Analog Devices

부품명 AD679JN
상세설명  14-Bit 128 kSPS Complete Sampling ADC
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AD679
REV. C
–6–
PIN DESCRIPTION
28-Pin
44-Lead
DIP
JLCC
Symbol
Pin No.
Pin No.
Type
Name and Function
AGND
7
11
P
Analog Ground. This is the ground return for AIN only.
AIN
6
10
AI
Analog Signal Input.
BIPOFF
10
15
AI
Bipolar Offset. Connect to AGND for +10 V input unipolar mode and straight
binary output coding. Connect to REFOUT for ± 5 V input bipolar mode and
twos complement binary output coding.
CS
4
6
DI
Chip Select. Active LOW.
DGND
12, 14
23
P
Digital Ground.
DB7–DB0
26–19
40, 39, 37, 36,
DO
Data Bits. These pins provide all 14 bits in two bytes (8+6 bits). Active HIGH.
35, 34, 33, 31
EOC
27
42
DO
End-of-Convert. EOC goes LOW when a conversion starts and goes HIGH
when the conversion finishes. In asynchronous mode, EOC is an open drain
output and requires an external 3 k
Ω pull-up resistor. See EOCEN and SYNC
pins for information on EOC gating.
EOCEN
1
1
DI
End-of-Convert Enable. Enables EOC pin. Active LOW.
HBE
15
25
DI
High Byte Enable. If LOW, output contains high byte. If HIGH, output
contains low byte (corresponding to the most recently read high byte).
OE
2
3
DI
Output Enable. A down-going transition on OE enables DB7–DB0. Gated with
CS
. Active LOW.
REFIN
9
14
AI
Reference Input. +5 V input gives 10 V full-scale range.
REFOUT
8
12
AO
+5 V Reference Output. Tied to REFIN for normal operation.
SC
3
5
DI
Start Convert. Active LOW. See SYNC pin for gating.
SYNC
13
21
DI
SYNC Control. If tied to VDD (synchronous mode), SC and EOCEN are gated
by CS. If tied to DGND (asynchronous mode), SC and EOCEN are indepen-
dent of CS, and EOC is an open drain output. EOC requires an external 3 k
pull-up resistor in asynchronous mode.
VCC
11
17
P
+12 V Analog Power.
VEE
5
8
P
–12 V Analog Power.
VDD
28
43
P
+5 V Digital Power.
16
U
Tie to DGND.
17–18
2, 4, 7, 9, 13,
U
These pins are unused and should be connected to DGND or VDD.
16, 18, 19, 20,
22, 24, 26, 27,
28, 29, 30, 32,
38, 41, 44
Type: AI = Analog Input. AO = Analog Output. DI = Digital Input (TTL and 5 V CMOS compatible). DO = Digital Output (TTL and 5 V CMOS compatible).
All DO pins are three-state drivers. P = Power. U = Unused.
PIN CONFIGURATION
DIP Package
JLCC Package


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