전자부품 데이터시트 검색엔진 |
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AD725 데이터시트(PDF) 10 Page - Analog Devices |
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AD725 데이터시트(HTML) 10 Page - Analog Devices |
10 / 20 page REV. 0 –10– AD725 Table I. Timing Description (See Figure 18) Symbol Name Description NTSC1 PAL2 tSW Sync Width Input valid sync width for burst Min 2.8 µs Min 3.3 µs insertion (user-controlled). Max 5.3 µs Max 5.4 µs tSB Sync to Blanking Minimum sync to color delay End (user-controlled). Min 8.2 µs Min 8.1 µs tSM Sync to Modulator Delay to modulator clamp start. Restore 392 ns 298 ns tMW Modulator Restore Length of modulator offset clamp Width (no chroma during this period). 140 ns 113 ns tSR Sync to RGB DC Delay to input clamping start. Restore 5.4 µs 5.6 µs tRW DC Restore Width Length of input clamp (no RGB response during this period). 2.5 µs 2.3 µs tSD Sync to Delay Line Delay to start of delay line Reset clock reset. 5.7 µs 5.8 µs tDW Delay Line Reset Length of delay line clock reset Width (no luma response during this period), also burst gate. 2.5 µs 2.3 µs tSS Sync Input to Luma Delay from sync input assertion Sync Output to sync in LUMA output. typ 310 ns typ 265 ns tBY Blanking End to Delay from RGB input assertion LUMA Start to LUMA output response. typ 340 ns typ 280 ns tSC Sync to Colorburst Delay from valid horizontal sync start to CRMA colorburst output. typ 5.8 µs typ 5.9 µs tBC Blanking End to Delay from RGB input assertion CRMA Start to CRMA output response. typ 360 ns typ 300 ns NOTES 1Input clock = 14.318180 MHz, STND pin = logic high. 2Input cock = 17.734475 MHz, STND pin = logic low. tSW tSB tSM tMW tSR tRW tSD tDW tSS tBY tSC tBC HSYNC/VSYNC (USER INPUTS) RIN/GIN BIN (USER INPUTS) MODULATOR RESTORE INPUT CLAMPS BURST FLAG/ DELAY LINE RESET LUMA CRMA Figure 18. Timing Diagram (Not to Scale) |
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