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AD7399BRU-REEL7 데이터시트(PDF) 6 Page - Analog Devices |
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AD7399BRU-REEL7 데이터시트(HTML) 6 Page - Analog Devices |
6 / 16 page REV. 0 AD7398/AD7399 –6– Table I. Control Logic Truth Table CS CLK LDAC Serial Shift Register Function Input Register Function DAC Register H X H No Effect No Effect No Effect L L H No Effect No Effect No Effect L ↑+ H Shift-Register-Data Advanced One Bit Latched Latched L H H No Effect Latched Latched ↑+ L/H H No Effect Updated with SR Contents Latched H X L No Effect Latched Transparent HX ↑+ No Effect Latched Latched NOTES 1. ↑+ Positive logic transition; ↓– Negative logic transition; X Don’t Care; SR shift register. 2. At power ON, both the Input Register and the DAC Register are loaded with all zeros. 3 . During Power Shutdown, reprogramming of any internal registers can take place, but the output amplifiers will not produce the new values until the part is taken out of Shutdown mode. 4. LDAC input is a level-sensitive input that controls the four DAC registers. Table II. AD7398 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format MSB LSB Bit Position B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 AD7398 SA SD A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NOTE Bit positions B14 and B15 are power shutdown control Bits SD and SA. If SA is set to Logic 1, all DACs are placed in the power shutdown mode. If SD is set to Logic 1, the address decoded by Bits B12 and B13 (A0 and A1) determine the DAC channel that will be placed in the power shutdown state. Table III. AD7399 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format MSB LSB Bit Position B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 AD7399 SA SD A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NOTE Bit positions B12 and B13 are power shutdown control Bits SD and SA. If SA is set to Logic 1, all DACs are placed in the power shutdown mode. If SD is set to Logic 1, the address decoded by Bits B10 and B11 (A0 and A1) determine the DAC channel that will be placed in the power shutdown state. Table IV. AD7398/AD7399 Address Decode Control SA SD A1 A0 DAC Channel Affected 1 X X X All DACs Shutdown 0100 DAC A Shutdown 0101 DAC B Shutdown 0110 DAC C Shutdown 0111 DAC D Shutdown 0000 DAC A Input Register Decoded 0001 DAC B Input Register Decoded 0010 DAC C Input Register Decoded 0011 DAC D Input Register Decoded |
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