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AD7538AQ 데이터시트(PDF) 6 Page - Analog Devices |
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AD7538AQ 데이터시트(HTML) 6 Page - Analog Devices |
6 / 8 page AD7538 REV. A –6– For zero offset adjustment, the DAC register is loaded with all 0s and amplifier offset (VOS) adjusted so that VOUT is 0 V. Ad- justing VOUT to 0 V is not necessary in many applications, but it is recommended that VOS be no greater than (25 × 10 –6) (V REF) to maintain specified DAC accuracy (see Applications Hints). Full-scale trimming is accomplished by loading the DAC register with all 1s and adjusting R1 so that VOUTA = –VIN (16383/16384). For high temperature operation, resistors and potentiometers should have a low Temperature Coefficient. In many applica- tions, because of the excellent Gain T.C. and Gain Error speci- fications of the AD7538, Gain Error trimming is not necessary. In fixed reference applications, full scale can also be adjusted by omitting R1 and R2 and trimming the reference voltage magnitude. BIPOLAR OPERATION (4-QUADRANT MULTIPLICATION) The recommended circuit diagram for bipolar operation is shown in Figure 5. Offset binary coding is used. The code table for Figure 5 is given in Table II. With the DAC loaded to 10 0000 0000 0000, adjust R1 for VO = 0 V. Alternatively, one can omit R1 and R2 and adjust the ratio of R5 and R6 for VO = 0 V. Full-scale trimming can be accomplished by adjusting the amplitude of VIN or by varying the value of R7. The values given for R1, R2 are the minimum necessary to cali- brate the system for resistors, R5, R6, R7 ratio matched to 0.1%. System linearity error is independent of resistor ratio matching and is affected by DAC linearity error only. When operating over a wide temperature range, it is important that the resistors be of the same type so that their temperature coefficients match. For further information sec “CMOS DAC Application Guide”, 3rd Edition, Publication Number G872b-8-1/89 available from Analog Devices. Figure 5. Bipolar Operation LOW LEAKAGE CONFIGURATION For CMOS Multiplying D/A converters, as the device is oper- ated at higher temperatures, the output leakage current in- creases. For a 14-bit resolution system, this can be a significant source of error. The AD7538 features a leakage reduction con- figuration (U.S. Patent No. 4,590,456) to keep the leakage cur- rent low over an extended temperature range. One may operate the device with or without this configuration. If VSS (Pin 24) is tied to AGND then the DAC will exhibit normal output leakage current at high temperatures. To use the low leakage facility, Table II. Bipolar Code Table for Offset Binary Circuit of Figure 5. Binary Number In DAC Register Analog Output VOUT MSB LSB 11 1111 1111 1111 +V IN 8191 8192 10 0000 0000 0001 +V IN 1 8192 10 0000 0000 0000 0 V 01 1111 1111 1111 –VIN 1 8192 00 0000 0000 0000 –VIN 8191 8192 VSS should be tied to a voltage of approximately –0.3 V as in Figures 4 and 5. A simple resistor divider (R3, R4) produces ap- proximately –300 mV from –15 V. The capacitor C2 in parallel with R3 is an integral part of the low leakage configuration and must be 4.7 µF or greater. Figure 6 is a plot of leakage current versus temperature for both conditions. It clearly shows the im- provement gained by using the low leakage configuration. Figure 6. Graph of Typical Leakage Current vs. Temperature for AD7538 PROGRAMMABLE GAIN AMPLIFIER The circuit shown in Figure 7 provides a programmable gain amplifier (PGA). In it the DAC behaves as a programmable resistance and thus allows the circuit gain to be digitally controlled. Figure 7. Programmable Gain Amplifier (PGA) |
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