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AD7476SRTZ-REEL7 데이터시트(PDF) 10 Page - Analog Devices

부품명 AD7476SRTZ-REEL7
상세설명  1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SOT-23
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REV. D
–10–
AD7476/AD7477/AD7478
CIRCUIT INFORMATION
The AD7476/AD7477/AD7478 are, respectively, 12-bit, 10-bit,
and 8-bit, fast, micropower, single-supply ADCs. The parts can be
operated from a 2.35 V to 5.25 V supply. When operated from
either a 5 V supply or a 3 V supply, the AD7476/AD7477/AD7478
are capable of throughput rates of 1 MSPS when provided with
a 20 MHz clock.
The AD7476/AD7477/AD7478 provide the user with an on-chip,
track-and-hold ADC, and a serial interface housed in a tiny
6-lead SOT-23 package, which offers the user considerable
space saving advantages over alternative solutions. The serial
clock input accesses data from the part and also provides the
clock source for the successive-approximation ADC. The analog
input range is 0 V to VDD. An external reference is not required
for the ADC, nor is there a reference on-chip. The reference for
the AD7476/AD7477/AD7478 is derived from the power supply
and thus gives the widest dynamic input range.
The AD7476/AD7477/AD7478 also feature a power-down option
to save power between conversions. The power-down feature is
implemented across the standard serial interface as described in
the Modes of Operation section.
CONVERTER OPERATION
The AD7476/AD7477/AD7478 are successive-approximation
analog-to-digital converters based around a charge redistribution
DAC. Figures 2 and 3 show simplified schematics of the ADC.
Figure 2 shows the ADC during its acquisition phase. SW2 is
closed and SW1 is in position A, the comparator is held in a
balanced condition, and the sampling capacitor acquires the
signal on VIN.
CHARGE
REDISTRIBUTION
DAC
SW2
VDD/2
SAMPLING
CAPACITOR
VIN
SW1
A
B
AGND
ACQUISITION
PHASE
CONTROL
LOGIC
COMPARATOR
Figure 2. ADC Acquisition Phase
When the ADC starts a conversion (see Figure 3), SW2 will open
and SW1 will move to Position B, causing the comparator to
become unbalanced. The Control Logic and the Charge Redistri-
bution DAC are used to add and subtract fixed amounts of charge
from the sampling capacitor to bring the comparator back into a
balanced condition. When the comparator is rebalanced, the
conversion is complete. The Control Logic generates the ADC
output code. Figures 4 and 5 show the ADC transfer function.
CHARGE
REDISTRIBUTION
DAC
SW2
VDD/2
SAMPLING
CAPACITOR
VIN
SW1
A
B
AGND
CONVERSION
PHASE
CONTROL
LOGIC
COMPARATOR
Figure 3. ADC Conversion Phase
ADC TRANSFER FUNCTION
The output coding of the AD7476/AD7477/AD7478 is straight
binary. For the AD7476/AD7477, designed code transitions
occur midway between successive integer LSB values (i.e.,
1/2 LSB, 3/2 LSB, and so on). The LSB size for the AD7476
is VDD/4096 and the LSB size for the AD7477 is VDD/1024. The
ideal transfer characteristic for the AD7476/AD7477 is shown
in Figure 4.
For the AD7478, designed code transitions occur midway between
successive integer LSB values (i.e., 1 LSB, 2 LSB, and so on).
The LSB size for the AD7478 is VDD/256. The ideal transfer
characteristic for the AD7478 is shown in Figure 5.
1LSB = VDD/4096 (AD7476)
1LSB = VDD/1024 (AD7477)
ANALOG INPUT
111 ... 111
0V
0.5LSB
VDD–1.5LSB
111 ... 110
111 ... 000
011 ... 111
000 ... 010
000 ... 001
000 ... 000
Figure 4. Transfer Characteristic for the AD7476/AD7477
ANALOG INPUT
111 ... 111
0V
1LSB
VDD–1LSB
111 ... 110
111 ... 000
011 ... 111
000 ... 010
000 ... 001
000 ... 000
1LSB = VDD/256 (AD7478)
Figure 5. Transfer Characteristic for AD7478
TYPICAL CONNECTION DIAGRAM
Figure 6 shows a typical connection diagram for the AD7476/
AD7477/AD7478. VREF is taken internally from VDD and as
such, VDD should be well decoupled. This provides an analog
input range of 0 V to VDD. The conversion result is output in a
16-bit word with four leading zeros followed by the MSB of the
12-bit, 10-bit, or 8-bit result. The 10-bit result from the AD7477
will be followed by two trailing zeros. The 8-bit result from
the AD7478 will be followed by four trailing zeros.


유사한 부품 번호 - AD7476SRTZ-REEL7

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