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AD7707BR 데이터시트(PDF) 3 Page - Analog Devices |
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AD7707BR 데이터시트(HTML) 3 Page - Analog Devices |
3 / 40 page REV. A –3– AD7707 Parameter B Version 1 Units Conditions/Comments HIGH LEVEL ANALOG INPUT CHANNEL (AIN3) AIN3 is with respect to HICOM. AIN3 Voltage Range +10 V max –10 V min Normal Mode 50 Hz Rejection 78 dB typ For Filter Notches of 10 Hz, 25 Hz, 50 Hz, ± 0.02 × f NOTCH Normal Mode 60 Hz Rejection 78 dB typ For Filter Notches of 10 Hz, 20 Hz, 60 Hz, ± 0.02 × f NOTCH AIN3 Input Sampling Rate, fS GAIN × f CLKIN/64 For Gains of 1 to 4 fCLKIN/8 For Gains of 8 to 128 AIN3 Input Impedance 2 27 k Ω min Typically 30 k Ω ±10%; Typical Resistor Tempco is –30 ppm/°C AIN3 Sampling Capacitance 2 10 pF max VBIAS Input Range 0 V/AVDD V min/max Typically = REFIN(+) = 2.5 V LOGIC INPUTS Input Current All Inputs Except MCLK IN ±1 µA max Typically ±20 nA MCLK ±10 µA max Typically ±2 µA All Inputs Except SCLK and MCLK IN VINL, Input Low Voltage 0.8 V max DVDD = 5 V 0.4 V max DVDD = 3 V VINH, Input High Voltage 2.0 V min DVDD = 3 V and 5 V SCLK Only (Schmitt Triggered Input) DVDD = 5 V Nominal VT+ 1.4/3 V min/V max VT– 0.8/1.4 V min/V max VT+ – VT– 0.4/0.8 V min/V max SCLK Only (Schmitt Triggered Input) DVDD = 3 V Nominal VT+ 1/2.5 V min/V max VT– 0.4/1.1 V min/V max VT+ – VT– 0.375/0.8 V min/V max MCLK IN Only DVDD = 5 V Nominal VINL, Input Low Voltage 0.8 V max VINH, Input High Voltage 3.5 V min MCLK IN Only DVDD = 3 V Nominal VINL, Input Low Voltage 0.4 V max VINH, Input High Voltage 2.5 V min LOGIC OUTPUTS (Including MCLK OUT) VOL, Output Low Voltage 0.4 V max ISINK = 800 µA Except for MCLK OUT. 13 DV DD = 5 V 0.4 V max ISINK = 100 µA Except for MCLK OUT. 13 DV DD = 3 V VOH, Output High Voltage 4 V min ISOURCE = 200 µA Except for MCLK OUT. 13 DV DD = 5 V DVDD – 0.6 V min ISOURCE = 100 µA Except for MCLK OUT. 13 DV DD = 3 V Floating State Leakage Current ±10 µA max Floating State Output Capacitance 14 9 pF typ Data Output Coding Binary Unipolar Mode Offset Binary Bipolar Mode SYSTEM CALIBRATION Low Level Input Channels (AIN1 and AIN2) Positive Full-Scale Calibration Limit 15 (1.05 × V REF)/GAIN V max GAIN Is The Selected PGA Gain (1 to 128) Negative Full-Scale Calibration Limit 15 – (1.05 × V REF)/GAIN V max GAIN Is The Selected PGA Gain (1 to 128) Offset Calibration Limit 16 – (1.05 × V REF)/GAIN V max GAIN Is The Selected PGA Gain (1 to 128) Input Span 16 (0.8 × V REF)/GAIN V min GAIN Is The Selected PGA Gain (1 to 128) (2.1 × V REF)/GAIN V max GAIN Is The Selected PGA Gain (1 to 128) High Level Input Channels (AIN3) Positive Full-Scale Calibration Limit 15 (8.4 × V REF)/GAIN V max GAIN Is The Selected PGA Gain (1 to 128) Negative Full-Scale Calibration Limit 15 – (8.4 × V REF)/GAIN V max GAIN Is The Selected PGA Gain (1 to 128) Offset Calibration Limit 16 – (8.4 × V REF)/GAIN V max GAIN Is The Selected PGA Gain (1 to 128) Input Span 16 (6.4 × V REF)/GAIN V min GAIN Is The Selected PGA Gain (1 to 128) (16.8 × V REF)/GAIN V max GAIN Is The Selected PGA Gain (1 to 128) POWER REQUIREMENTS Power Supply Voltages AVDD Voltage +2.7 to +3.3 or +4.75 to +5.25 V For Specified Performance DVDD Voltage +2.7 to +5.25 V For Specified Performance Power Supply Currents AVDD Current AVDD = 3 V or 5 V. Gain = 1 to 4 0.27 mA max Typically 0.22 mA. BUF = 0. fCLK IN = 1 MHz or 2.4576 MHz 0.6 mA max Typically 0.45 mA. BUF = 1. fCLK IN = 1 MHz or 2.4576 MHz AVDD = 3 V or 5 V. Gain = 8 to 128 0.5 mA max Typically 0.38 mA. BUF = 0. fCLK IN = 2.4576 MHz 1.1 mA max Typically 0.81 mA. BUF = 1. fCLK IN = 2.4576 MHz |
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