AD7813

–6–

REV. B

CIRCUIT DESCRIPTION

Converter Operation

The AD7813 is a successive approximation analog-to-digital

converter based around a charge redistribution DAC. The ADC

ures 2 and 3 below show simplified schematics of the ADC.

Figure 2 shows the ADC during its acquisition phase. SW2 is

closed and SW1 is in Position A, the comparator is held in a

balanced condition and the sampling capacitor acquires the

CHARGE

REDISTRIBUTION

DAC

CONTROL

LOGIC

CLOCK

OSC

COMPARATOR

SW2

ACQUISITION

PHASE

SAMPLING

CAPACITOR

SW1

A

B

AGND

Figure 2. ADC Track Phase

When the ADC starts a conversion (see Figure 3), SW2 will

open and SW1 will move to Position B, causing the comparator

to become unbalanced. The Control Logic and the Charge

Redistribution DAC are used to add and subtract fixed amounts

of charge from the sampling capacitor so as to bring the com-

parator back into a balanced condition. When the comparator is

rebalanced the conversion is complete. The Control Logic gen-

erates the ADC output code. Figure 7 shows the ADC transfer

function.

CHARGE

REDISTRIBUTION

DAC

CONTROL

LOGIC

CLOCK

OSC

COMPARATOR

SW2

CONVERSION

PHASE

SAMPLING

CAPACITOR

SW1

A

B

AGND

Figure 3. ADC Conversion Phase

TYPICAL CONNECTION DIAGRAM

Figure 4 shows a typical connection diagram for the AD7813. The

parallel interface is implemented using an 8-bit data bus, the

falling edge of

CONVST brings the BUSY signal high, and at

the end of conversion the falling edge of BUSY is used to ini-

tiate an Interrupt Service Routine (ISR) on a microprocessor—

up in a low current mode, i.e., power-down. A rising edge on an

internal

CONVST input will cause the part to power up—see

Power-Up Times. If power consumption is of concern, the

automatic power-down at the end of a conversion should be

used to improve power performance. See Power vs. Throughput

Rate section of the data sheet.

BUSY

RD

CS

CONVST

DB0-DB7

GND

AD7813

C/ P

PARALLEL

INTERFACE

INPUT

0.1 F

10 F

SUPPLY

+2.7V TO +5.5V

Figure 4. Typical Connection Diagram

Analog Input

Figure 5 shows an equivalent circuit of the analog input struc-

ture of the AD7813. The two diodes, D1 and D2, provide ESD

protection for the analog inputs. Care must be taken to ensure

that the analog input signal never exceeds the supply rails by

more than 200 mV. This will cause these diodes to become

forward biased and start conducting current into the substrate.

The maximum current these diodes can conduct without caus-

ing irreversible damage to the part is 20 mA. The capacitor C2,

in Figure 5, is typically about 4 pF and can be primarily attrib-

uted to pin capacitance. The resistor R1 is a lumped component

made up of the on resistance of a multiplexer and a switch. This

resistor is typically about 125

Ω. The capacitor C1 is the ADC

sampling capacitor and has a capacitance of 3.5 pF.

C2

4pF

D1

D2

R1

125

C1

3.5pF

CONVERT PHASE – SWITCH OPEN

TRACK PHASE – SWITCH CLOSED

Figure 5. Equivalent Analog Input Circuit

DC Acquisition Time

The ADC starts a new acquisition phase at the end of a conver-

sion and ends on the falling edge of the

CONVST signal. At the

end of a conversion there is a settling time associated with the

sampling circuit. This settling time lasts approximately 100 ns.

time; therefore, the minimum acquisition time needed is ap-

proximately 100 ns.

Figure 6 shows the equivalent charging circuit for the sampling

capacitor when the ADC is in its acquisition phase. R2 repre-

sents the source impedance of a buffer amplifier or resistive

network, R1 is an internal multiplexer resistance and C1 is the

sampling capacitor.

R1

125

R2

C1

3.5pF

Figure 6. Equivalent Sampling Circuit