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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AD7896AR 데이터시트(PDF) 3 Page - Analog Devices |
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AD7896AR 데이터시트(HTML) 3 Page - Analog Devices |
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3 / 12 page  AD7896 REV. B –3– A, B J S Parameter Versions Version Version Units Test Conditions/Comments t1 40 40 40 ns min CONVST Pulse Width t2 40 2 40 2 45 2 ns min SCLK High Pulse Width t3 40 2 40 2 45 2 ns min SCLK Low Pulse Width t4 Data Access Time After Falling Edge of SCLK 60 3 60 3 70 3 ns max VDD = 5 V ± 10% 100 3 100 3 110 3 ns max VDD = 2.7 V to +3.6 V t5 10 10 10 ns min Data Hold Time After Falling Edge of SCLK t6 50 4 50 4 50 4 ns max Bus Relinquish Time After Falling Edge of SCLK NOTES 1Sample tested at +25 °C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of V DD) and timed from a voltage level of +1.4 V. 2The SCLK maximum frequency is 10 MHz. Care must be taken when interfacing to account for the data access time, t 4, and the setup time required for the user's processor. These two times will determine the maximum SCLK frequency that the user's system can operate with. See Serial Interface section for more information. 3Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.0 V. 4Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 6, quoted in the timing characteristics is the true bus relinquish time of the part and as such is independent of external bus loading capacitances. TIMING CHARACTERISTICS1 (VDD = +2.7 V to +5.5 V, AGND = DGND = 0 V) ABSOLUTE MAXIMUM RATINGS* (TA = +25 °C unless otherwise noted) VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V VDD to DGND. . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V Analog Input Voltage to AGND . . . . . . –0.3 V to VDD + 0.3 V Digital Input Voltage to DGND . . . . . . –0.3 V to VDD + 0.3 V Digital Output Voltage to DGND . . . . . –0.3 V to VDD + 0.3 V Operating Temperature Range Commercial (J Version) . . . . . . . . . . . . . . . . . 0 °C to +70°C Industrial (A, B Versions) . . . . . . . . . . . . . . . –40 °C to +85°C Extended (S Version) . . . . . . . . . . . . . . . . . –55 °C to +125°C Storage Temperature Range . . . . . . . . . . . . . –65 °C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150 °C Plastic DIP Package, Power Dissipation . . . . . . . . . . . 450 mW θ JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 125 °C/W θ JC Thermal Impedance. . . . . . . . . . . . . . . . . . . . . . 50 °C/W Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +260 °C SOIC Package, Power Dissipation . . . . . . . . . . . . . . . . 450 mW θ JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 160 °C/W θ JC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75 °C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215 °C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220 °C ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >4000 V *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. +1.6V 2.0mA 2.0mA 50pF TO OUTPUT PIN Figure 1. Load Circuit for Access Time and Bus Relinquish Time |
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유사한 설명 - AD7896AR |
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