AD8009

–11–

REV. B

Driving a Capacitive Load

A capacitive load, like that presented by some A/D converters,

can sometimes be a challenge for an op amp to drive depending

on the architecture of the op amp. Most of the problem is

caused by the pole created by the output impedance of the op

amp and the capacitor that is driven. This creates extra phase

shift that can eventually cause the op amp to become unstable.

One way to prevent instability and improve settling time when

driving a capacitor is to insert a resistor in series between the op

amp output and the capacitor. The feedback resistor is still

connected directly to the output of the op amp, while the series

resistor provides some isolation of the capacitive load from the

op amp output.

10 F

+

0.1 F

0.001 F

10 F

+

0.1 F

0.001 F

AD8009

49.9

+5V

–5V

3

2

4

50pF

7

6

Figure 39. Capacitive Load Drive Circuit

Figure 39 shows such a circuit with an AD8009 driving a 50 pF

to 42.2

Ω will minimize the 0.1% settling time with a 2 V step at

the output. The 0.1% settling time was measured to be 40 ns with

this circuit.

capacitive loads. Of course, a larger capacitance will always

require more time for settling to a given accuracy than a smaller

At best, a given RC combination will require about 7 time

constants by itself to settle to 0.1%, so a limit will be reached

where too large a capacitance cannot be driven by a given

op amp and still meet the system’s required settling time

specification.