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AD8138ARM-REEL 데이터시트(PDF) 11 Page - Analog Devices |
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AD8138ARM-REEL 데이터시트(HTML) 11 Page - Analog Devices |
11 / 16 page REV. E AD8138 –11– The power supply pins should be bypassed as close as possible to the device to the nearby ground plane. Good high frequency ceramic chip capacitors should be used. This bypassing should be done with a capacitance value of 0.01 mF to 0.1 mF for each supply. Further away, low frequency bypassing should be provided with 10 mF tantalum capacitors from each supply to ground. The signal routing should be short and direct to avoid parasitic effects. Wherever there are complementary signals, a symmetrical layout should be provided to the extent possible to maximize the balance performance. When running differential signals over a long distance, the traces on the PCB should be close together or any differential wiring should be twisted together to minimize the area of the loop that is formed. This will reduce the radiated energy and make the circuit less susceptible to interference. BALANCED TRANSFORMER DRIVER Transformers are among the oldest devices used to perform a single-ended-to-differential conversion (and vice versa). Trans- formers also can perform the additional functions of galvanic isolation, step-up or step-down of voltages, and impedance transformation. For these reasons, transformers will always find uses in certain applications. However, when driving a transformer single-endedly and then looking at its output, there is a fundamental imbalance due to the parasitics inherent in the transformer. The primary (or driven) side of the transformer has one side at dc potential (usually ground), while the other side is driven. This can cause problems in systems that require good balance of the transformer’s differential output signals. If the interwinding capacitance (CSTRAY) is assumed to be uni- formly distributed, a signal from the driving source will couple to the secondary output terminal that is closest to the primary’s driven side. On the other hand, no signal will be coupled to the opposite terminal of the secondary because its nearest primary terminal is not driven (see Figure 3). The exact amount of this imbalance will depend on the particular parasitics of the trans- former, but will mostly be a problem at higher frequencies. The balance of a differential circuit can be measured by connecting an equal-valued resistive voltage divider across the differential outputs and then measuring the center point of the circuit with respect to ground. Since the two differential outputs are supposed to be of equal amplitude, but 180 opposite phase, there should be no signal present for perfectly balanced outputs. The circuit in Figure 3 shows a Minicircuits T1-6T transformer connected with its primary driven single-endedly and the second- ary connected with a precision voltage divider across its terminals. The voltage divider is made up of two 500 W, 0.005% preci- sion resistors. The voltage VUNBAL, which is also equal to the ac common-mode voltage, is a measure of how closely the outputs are balanced. The plots in Figure 5 compare the transformer being driven single-endedly by a signal generator and being driven differen- tially using an AD8138. The top signal trace of Figure 5 shows the balance of the single-ended configuration, while the bottom shows the differentially driven balance response. The 100 MHz balance is 35 dB better when using the AD8138. The well-balanced outputs of the AD8138 will provide a drive signal to each of the transformer’s primary inputs that are of equal amplitude and 180 out of phase. Thus, depending on how the polarity of the secondary is connected, the signals that conduct across the interwinding capacitance will either both assist the transformer’s secondary signal equally, or both buck the secondary signals. In either case, the parasitic effect will be symmetrical and provide a well balanced transformer output (see Figure 5). PRIMARY CSTRAY CSTRAY NO SIGNAL IS COUPLED ON THIS SIDE SIGNAL WILL BE COUPLED ON THIS SIDE VIA CSTRAY 52.3 SECONDARY VDIFF 500 0.005% 500 0.005% VUNBAL Figure 3. Transformer Single-Ended-to-Differential Converter Is Inherently Imbalanced VDIFF 500 0.005% 500 0.005% VUNBAL CSTRAY CSTRAY AD8138 +IN –IN 499 OUT+ OUT– 499 499 499 49.9 49.9 Figure 4. AD8138 Forms a Balanced Transformer Driver FREQUENCY – MHz 0 0.3 500 110 100 –20 –40 –60 –80 –100 VUNBAL, DIFFERENTIAL DRIVE VUNBAL, FOR TRANSFORMER WITH SINGLE-ENDED DRIVE Figure 5. Output Balance Error for Circuits of Figures 3 and 4 |
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