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AD8320ARP 데이터시트(PDF) 9 Page - Analog Devices |
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AD8320ARP 데이터시트(HTML) 9 Page - Analog Devices |
9 / 20 page AD8320 –9– REV. 0 OPERATIONAL DESCRIPTION The AD8320 is a digitally controlled variable gain power ampli- fier that is optimized for driving 75 Ω cable. A multifunctional bipolar device on single silicon, it incorporates all the analog features necessary to accommodate reverse path (upstream) high speed (5 MHz to 65 MHz) cable data modem and cable tele- phony requirements. The AD8320 has an overall gain range of 36 dB (–10 dB to 26 dB) and is capable of greater than 100 MHz of operation at output signal levels exceeding 18 dBm. Overall, when considering the device’s wide gain range, low distortion, wide bandwidth and variable load drive, the device can be used in many variable gain block applications. The digitally programmable gain is controlled by the three wire “SPI” compatible inputs. These inputs are called SDATA (serial data input port), DATEN (data enable low input port) and CLK (clock input port). See Pin Function Descriptions and Functional Block diagram. The AD8320 is programmed by an 8-bit “attenuator” word. These eight bits determine the 256 programmable gain settings. See attenuator core description below. The gain is linear in V/V/LSB and can be described by the following equation: AV = 0.316 + 0.077 × Code (R L = 75 Ω) where code is the decimal equivalent of the 8-bit word. For ex- ample, if all 8 bits are at a logic “1,” the decimal equivalent is 255 and AV equals 19.95 V/V or 26 dB. The gain scaling factor is 0.077 V/V/LSB, with an offset of 0.316 V/V (–10.0 dB). Fig- ure 40 shows the linear gain versus decimal code and Figure 41 shows the gain in dB versus decimal code. Note the nonlin- earity that results when viewed in dB versus code. The dB step size increases as the attenuation increases (i.e., gain decreases) and reaches a maximum step size of approximately 1.9 dB (gain change between 01 and 00 decimal). –2 GAIN – Code – Decimal 0 0 256 32 64 96 128 160 192 224 22 16 12 8 6 20 18 14 10 4 POWER-DOWN POWER-UP 2 AV = 0.316 + 0.077 CODE Figure 40. Linear Gain vs. Gain Control The AD8320 is composed of three analog functions in the power- up or forward mode (Figure 42). The input inverter/buffer amplifier provides single-ended to differential output conver- sion. The output signals are nominally 180 degrees out of phase and equal in amplitude with a differential voltage gain of 2 (6 dB). Maintaining close to 180 degrees and equal amplitude is re- quired for proper gain accuracy of the attenuator core over the specified operating frequency. The input buffer/inverter also provides equal dc voltages to the core inputs via the internal reference. This is required to ensure proper core linearity over the full specified power supply range (5 V to 12 V). –16 GAIN – Code – Decimal –8 0 256 32 64 96 128 160 192 224 24 8 0 32 16 AV = 20 LOG10 (0.316 + 0.077 CODE) Figure 41. Log Gain vs. Gain Control The attenuator core can be viewed as eight binarily weighted (differential in–differential out) transconductance (gm) stages with the “in phase” current outputs of all eight stages connected in parallel to their respective differential load resistors (not shown). The core differential output signals are also 180 degrees out of phase and equal in amplitude. The input stages are like- wise parallel, connected to the inverting input amplifier and buffer outputs as shown. Nine bits plus of accuracy is achieved for all gain settings over the specified frequency, supply voltage and temperature range. The actual total core GM × RL attenua- tion is determined by which combination of binarily weighted gm stages are selected by the data latch. With 8 bits, 256 levels of attenuation can be programmed. This results in a 36 dB attenuation range (0 dB to –36 dB). See gain equation above. POWER– DOWN SWITCH INTER. PWR AMP DATA SHIFT REGISTER DATA LATCH REVERSE AMP ATTENUATOR CORE GND VCC VREF VIN REFERENCE INV. BUF. DATEN CLK SDATA PD VOUT AD8320 Figure 42. Functional Block Diagram To update the AD8320 gain, the following digital load sequence is required. The attenuation setting is determined by the 8-bit word in the data latch. This 8-bit word is serially loaded (MSB first) into the shift register at each rising edge of the clock. See Figure 43. During this data load time (T), DATEN is low and the data latch is latched holding the previous (T – 1) data word keeping the attenuation level unchanged. After eight clock cycles the new data word is fully loaded and DATEN is switched high. This enables the data latch (becomes transpar- ent) and the loaded register data is passed to the attenuator with the updated gain value. Also at this DATEN transition, the internal clock is disabled, thus inhibiting new serial input data. |
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