REV. 0

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a

ADF4106

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

www.analog.com

Fax: 781/326-8703

© Analog Devices, Inc., 2001

PLL Frequency Synthesizer

FEATURES

6.0 GHz Bandwidth

2.7 V to 3.3 V Power Supply

Tuning Voltage in 3 V Systems

Programmable Dual Modulus Prescaler

8/9, 16/17, 32/33, 64/65

Programmable Charge Pump Currents

Programmable Anti-Backlash Pulsewidth

3-Wire Serial Interface

Analog and Digital Lock Detect

Hardware and Software Power-Down Mode

APPLICATIONS

Broadband Wireless Access

Instrumentation

Wireless LANS

Base Stations For Wireless Radio

FUNCTIONAL BLOCK DIAGRAM

14-BIT

R COUNTER

R COUNTER

LATCH

FUNCTION

LATCH

AB COUNTER

LATCH

24-BIT INPUT

REGISTER

22

14

CLK

DATA

LE

PHASE

FREQUENCY

DETECTOR

CHARGE

PUMP

REFERENCE

CPGND

CURRENT

SETTING 2

CURRENT

SETTING 1

CPI3 CPI2 CPI1

CPI6 CPI5 CPI4

LOCK

DETECT

CP

MUXOUT

HIGH Z

19

13-BIT

B COUNTER

PRESCALER

P/P + 1

6-BIT

A COUNTER

FROM

FUNCTION

LATCH

LOAD

LOAD

M3 M2 M1

MUX

6

N = BP + A

CE

AGND

DGND

ADF4106

13

GENERAL DESCRIPTION

The ADF4106 frequency synthesizer can be used to implement

local oscillators in the up-conversion and down-conversion

sections of wireless receivers and transmitters. It consists of a

low-noise digital PFD (Phase Frequency Detector), a precision

charge pump, a programmable reference divider, programmable

A and B counters and a dual-modulus prescaler (P/P + 1). The

A (6-bit) and B (13-bit) counters, in conjunction with the dual

modulus prescaler (P/P + 1), implement an N divider (N = BP + A).

In addition, the 14-bit reference counter (R Counter), allows

selectable REFIN frequencies at the PFD input. A complete

PLL (Phase-Locked Loop) can be implemented if the synthe-

sizer is used with an external loop filter and VCO (Voltage

Controlled Oscillator). Its very high bandwidth means that

frequency doublers can be eliminated in many high-frequency

systems, simplifying system architecture and lowering cost.