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ADF4117BCP 데이터시트(PDF) 9 Page - Analog Devices |
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ADF4117BCP 데이터시트(HTML) 9 Page - Analog Devices |
9 / 20 page ADF4116/ADF4117/ADF4118 –9– REV. 0 –60 –80 –90 –70 TEMPERATURE – C 0 20406080 100 VDD = 3V VP = 5V –100 Figure 19. ADF4118 Reference Spurs vs. Temperature (836 MHz, 30 kHz, 3 kHz) CIRCUIT DESCRIPTION REFERENCE INPUT SECTION The reference input stage is shown below in Figure 21. SW1 and SW2 are normally-closed switches. SW3 is normally-open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down. BUFFER TO R COUNTER REFIN 100k NC SW2 SW3 NO NC SW1 POWER-DOWN CONTROL Figure 21. Reference Input Stage RF INPUT STAGE The RF input stage is shown in Figure 22. It is followed by a 2- stage limiting amplifier to generate the CML clock levels needed for the prescaler. AVDD AGND 500 500 1.6V BIAS GENERATOR RFINA RFINB Figure 22. RF Input Stage PRESCALER (P/P + 1) The dual modulus prescale (P/P + 1), along with the A and B counters, enables the large division ratio, N, to be realized, (N = PB + A). The dual-modulus prescaler takes the CML clock from the RF input stage and divides it down to a manageable frequency for the CMOS A and B counters. The prescaler is programmable. It can be set in software to 8/9 for the ADF4116, and set to 32/33 for the ADF4117 and ADF4118. It is based on a synchronous 4/5 core. A AND B COUNTERS The A and B CMOS counters combine with the dual modulus prescaler to allow a wide ranging division ratio in the PLL feedback counter. The counters are specified to work when the prescaler output is 200 MHz or less. Pulse Swallow Function The A and B counters, in conjunction with the dual modulus prescaler make it possible to generate output frequencies which are spaced only by the Reference Frequency divided by R. The equation for the VCO frequency is as follows: fVCO = [(P × B) + A] × f REFIN/R fVCO Output Frequency of external voltage controlled oscilla- tor (VCO). P Preset modulus of dual modulus prescaler. B Preset Divide Ratio of binary 13-bit counter (3 to 8191). A Preset Divide Ratio of binary 5-bit swallow counter (0 to 31). fREFIN Output frequency of the external reference frequency oscillator. R Preset divide ratio of binary 14-bit programmable refer- ence counter (1 to 16383). R COUNTER The 14-bit R counter allows the input reference frequency to be divided down to produce the input clock to the phase frequency detector (PFD). Division ratios from 1 to 16,383 are allowed. 13-BIT B COUNTER 5-BIT A COUNTER PRESCALER P/P + 1 FROM RF INPUT STAGE MODULUS CONTROL N = BP + A LOAD LOAD TO PFD Figure 23. A and B Counters 0 0.0 PRESCALER OUTPUT FREQUENCY – MHz 50 100 150 200 0.5 1.0 1.5 2.0 2.5 3.0 Figure 20. DIDD vs. Prescaler Output Frequency (ADF4116, ADF4117, ADF4118) |
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