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ADMCF341-EVALKIT 데이터시트(PDF) 9 Page - Analog Devices

부품명 ADMCF341-EVALKIT
상세설명  DashDSP??28-Lead Flash Mixed-Signal DSP with Enhanced Analog Front End
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ADMCF341
–9–
PIN FUNCTION DESCRIPTION
The ADMCF341 is available in a 28-lead SOIC package.
Table I describes the pins.
Table I. Pin List
Pin Group
No. of Input/
Name
Pins
Output Function
RESET
1I
Processor Reset Input
SPORT1
1
2
I/O
Serial Port 1 Pins (DT1/FL1,
DR1, SCLK1/SCLK0
2)
SPORT0
1
5
I/O
Serial Port 0 Pins (DT0, DR0
TFSO, SCLK1/SCLK0
2)
CLKOUT
1
1
I/O
Processor Clock Output
CLKIN, XTAL
2
I, O
External Clock or Quartz
Crystal Connection Point
PORTA0–
9
I/O
Digital I/O Port Pins
PORTA8
1
AUX0–AUX1
1
2O
Auxiliary PWM Outputs
AH–CL
6
O
PWM Outputs
PWMTRIP
1I
PWM Trip Signal
ISENSE1–
3
I
ISENSE Inputs
ISENSE3
VAUX0–VAUX2 3
I
Auxiliary Analog Inputs
ICONST
1O
ADC Constant Current
Source
VDD
1I
Power Supply
GND
1
I
Ground
NOTES
1Multiplexed pins, individually selectable through PORTA_SELECT
and PORTA_DATA registers.
2SCLK1/SCLK0 multiplexed signals. Selectable through MODECTRL
Register Bit 4.
INTERRUPT OVERVIEW
The ADMCF341 can respond to 18 different interrupt sources
with minimal overhead, seven of which are internal DSP core
interrupts and 11 from the motor control peripherals. The
seven DSP core interrupts are SPORT1 receive (or
IRQ0) and
transmit (or
IRQ1), SPORT0 receive and transmit, the internal
timer, and two software interrupts. The motor control periph-
eral interrupts are the nine programmable I/Os and two from
the PWM (PWMSYNC pulse and
PWMTRIP). All motor
control interrupts are multiplexed into the DSP core through
the peripheral
IRQ2 interrupt. The interrupts are internally
prioritized and individually maskable. A detailed description of the
entire interrupt system of the ADMCF341 is presented later,
following a more detailed description of each peripheral block.
MEMORY MAP
The ADMCF341 has two distinct memory types: program and
data. In general, program memory contains user code and coef-
ficients, while the data memory is used to store variables and
data during program execution. Three kinds of program
memory are provided on the ADMCF341: RAM, ROM, and
FLASH. The motor control peripherals are memory mapped
into a region of the data memory space starting at 0x2000. The
complete program and data memory maps are given in Tables II
and III, respectively.
Table II. Program Memory Map
Memory
Address Range
Type
Function
0x0000–0x002F
RAM
Internal Vector Table
0x0030–0x01FF
RAM
User Program Memory
0x0200–0x07FF
Reserved
0x0800–0x17FF
ROM
Reserved Program Memory
0x1800–0x1FFF
Reserved
0x2000–0x20FF
FLASH
User Program Memory
Sector 0
0x2100–0x21FF
FLASH
User Program Memory
Sector 1
0x2200–0x2FFF
FLASH
User Program Memory
Sector 2
0x3000–0x3FFF
Reserved
Table III. Data Memory Map
Memory
Address Range
Type
Function
0x0000–0x1FFF
Reserved
0x2000–0x20FF
Memory Mapped Registers
0x2100–0x37FF
Reserved
0x3800–0x39FF
RAM
User Data Memory
0x3A00–0x3BFF
RAM
Reserved
0x3C00–0x3FFF
Memory Mapped Registers
FLASH MEMORY SUBSYSTEM
The ADMCF341 has 4K
24-bits of user-programmable,
nonvolatile flash memory. A flash programming utility is pro-
vided with the development tools, which perform the basic
device programming operations: erase, program, and verify.
The flash memory array is portioned into three asymmetrically
sized sectors of 256 words, 256 words, and 3584 words, labeled
sector 0, sector 1, and sector 2, respectively. These sectors are
mapped into external program memory address space.
Four flash memory interface registers are connected to the DSP.
These 16-bit registers are mapped into the register area of data
memory space. They are named flash memory control register
(FMCR), flash memory address register (FMAR), flash memory
data register low (FMDRL), and flash memory data register
high (FMDRH). These registers are diagrammed later in this
data sheet. They are used by the flash memory programming
utility. The user program may read these registers, but should
not modify them directly. The flash programming utility pro-
vides a complete interface to the flash memory.
It should be noted that the core accesses flash memory through
an external memory interface that multiplexes the program
memory and data memory buses into a single external bus.
Therefore, if more than one external transfer must be made in
the same instruction, there will be at least an overhead cycle
required.


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