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ADV7175A 데이터시트(PDF) 6 Page - Analog Devices |
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ADV7175A 데이터시트(HTML) 6 Page - Analog Devices |
6 / 52 page ADV7175A/ADV7176A –6– REV. B 5 V TIMING SPECIFICATIONS (VAA = 4.75 V – 5.25 V 1, V REF = 1.235 V RSET = 150 . All specifications TMIN to TMAX 2 unless otherwise noted.) Parameter Conditions Min Typ Max Units MPU PORT 3, 4 SCLOCK Frequency 0 100 kHz SCLOCK High Pulsewidth, t1 4.0 µs SCLOCK Low Pulsewidth, t2 4.7 µs Hold Time (Start Condition), t3 After This Period the First Clock Is Generated 4.0 µs Setup Time (Start Condition), t4 Relevant for Repeated Start Condition 4.7 µs Data Setup Time, t5 250 ns SDATA, SCLOCK Rise Time, t6 1 µs SDATA, SCLOCK Fall Time, t7 300 ns Setup Time (Stop Condition), t8 4.7 µs ANALOG OUTPUTS3, 5 Analog Output Delay 5ns DAC Analog Output Skew 0 ns CLOCK CONTROL AND PIXEL PORT 3, 6 FCLOCK 27 MHz Clock High Time, t9 8ns Clock Low Time, t10 8ns Data Setup Time, t11 3.5 ns Data Hold Time, t12 4ns Control Setup Time, t11 4ns Control Hold Time, t12 3ns Digital Output Access Time, t13 24 ns Digital Output Hold Time, t14 4ns Pipeline Delay, t15 37 Clock Cycles TELETEXT PORT 3, 7 Digital Output Access Time, t16 20 ns Data Setup Time, t17 1ns Data Hold Time, t18 2ns RESET CONTROL 3, 4 RESET Low Time 6 ns NOTES 1The max/min specifications are guaranteed over this range. 2Temperature range T MIN to TMAX: 0 oC to +70oC. 3TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. Analog output load ≤ 10 pF. 4Guaranteed by characterization. 5Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition. 6Pixel Port consists of the following: Pixel Inputs: P15–P0 Pixel Controls: HSYNC, FIELD/VSYNC, BLANK Clock Input: CLOCK 7Teletext Port consists of the following: Teletext Output: TTXREQ Teletext Input: TTX Specifications subject to change without notice. |
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