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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ADP1046AACPZ-R7 데이터시트(PDF) 61 Page - Analog Devices |
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ADP1046AACPZ-R7 데이터시트(HTML) 61 Page - Analog Devices |
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61 / 88 page  Data Sheet ADP1046A Rev. 0 | Page 61 of 88 Bits Bit Name R/W Description [2:0] Load line setting R/W These bits specify how much the output voltage decreases from nominal at full load. The amount of output resistance introduced can be calculated as follows (these bits specify the value of N): R OUT = 0.1 × VOUT_NOM × CS2 RSENSE/(CS2 Range × 2 N) For more information, see the Digital Load Line and Slew Rate section. Bit 2 Bit 1 Bit 0 Impedance Setting 0 0 0 Setting 0 0 0 1 Setting 1 0 1 0 Setting 2 0 1 1 Setting 3 1 0 0 Setting 4 1 0 1 Setting 5 1 1 0 Setting 6 1 1 1 Setting 7 Table 55. Register 0x37—Fast OVP Comparator Bits Bit Name R/W Description [7:6] Fast OVP debounce R/W These bits set the fast OVP debounce time. Bit 7 Bit 6 Debounce Time (µs) Min Typ Max 0 0 0 0 0 0 1 0.64 0.96 1.28 1 0 1.92 2.24 2.56 1 1 7.98 8 8.32 [5:0] Fast OVP threshold R/W These bits set the threshold for the fast OVP analog comparator. This threshold is programmable from 0.8 V to 1.6 V. Setting this value to 0x00 corresponds to a 0.8 V threshold. Setting this value to 0x3F corresponds to a 1.6 V threshold. Each LSB increments the threshold by 12.5 mV. The fast OVP threshold can be set using the following formula: Fast_OVP_Threshold = (Bits[5:0] × 0.8 V/63) + 0.8 V Table 56. Register 0x38—VS1 Trim Bits Bit Name R/W Description 7 Trim polarity R/W 1 = negative gain is introduced. 0 = positive gain is introduced. [6:0] VS1 trim R/W These bits set the amount of gain trim that is applied to the VS1 ADC reading. This register trims the voltage at the VS1 pin for external resistor tolerances. When there is 1 V on the VS1 pin, this register is trimmed until the VS1 voltage value (Register 0x15[15:4]) reads 2560 (0xA00). Table 57. Register 0x39—VS2 Trim Bits Bit Name R/W Description 7 Trim polarity R/W 1 = negative gain is introduced. 0 = positive gain is introduced. [6:0] VS2 trim R/W These bits set the amount of gain trim that is applied to the VS2 ADC reading. This register trims the voltage at the VS2 pin for external resistor tolerances. When there is 1 V on the VS2 pin, this register is trimmed until the VS2 voltage value (Register 0x16[15:4]) reads 2560 (0xA00). Table 58. Register 0x3A—VS3 Trim Bits Bit Name R/W Description 7 Trim polarity R/W 1 = negative gain is introduced. 0 = positive gain is introduced. [6:0] VS3 trim R/W These bits set the amount of gain trim that is applied to the VS3 ADC reading. This register trims the voltage at the VS3 pins for external resistor tolerances. When there is 1 V on each VS3 pin, this register is trimmed until the VS3 voltage value (Register 0x17[15:4]) reads 2560 (0xA00). The VS3 trim must be performed before the load OVP and load UVP trims are performed. |
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