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74ABT377CSJ 데이터시트(PDF) 1 Page - Fairchild Semiconductor |
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74ABT377CSJ 데이터시트(HTML) 1 Page - Fairchild Semiconductor |
1 / 9 page © 1999 Fairchild Semiconductor Corporation DS011550 www.fairchildsemi.com January 1993 Revised November 1999 74ABT377 Octal D-Type Flip-Flop with Clock Enable General Description The ABT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buff- ered Clock (CP) input loads all flip-flops simultaneously when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transi- tion, is transferred to the corresponding flip-flop’s Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation. Features s Clock enable for address and data synchronization applications s Eight edge-triggered D-type flip-flops s Buffered common clock s See ABT273 for master reset version s See ABT373 for transparent latch version s See ABT374 for 3-STATE version s Output sink capability of 64 mA, source capability of 32 mA s Guaranteed latchup protection s High impedance glitch free bus loading during entire power up and power down cycle s Non-destructive hot insertion capability s Disable time less than enable time to avoid bus contention Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Truth Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition I = LOW Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition Order Number Package Number Package Description 74ABT377CSC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body 74ABT377CSJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ABT377CMSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 74ABT377CMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pin Names Descriptions D0–D7 Data Inputs CE Clock Enable (Active LOW) CP Clock Pulse Input Q0–Q7 Data Outputs Operating Mode Inputs Output CP CE Dn Qn Load “1” Ih H Load “0” II L Hold h X No Change (Do Nothing) X H X No Change |
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