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74AC109SJ 데이터시트(PDF) 1 Page - Fairchild Semiconductor |
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74AC109SJ 데이터시트(HTML) 1 Page - Fairchild Semiconductor |
1 / 9 page © 2000 Fairchild Semiconductor Corporation DS009923 www.fairchildsemi.com November 1988 Revised August 2000 74AC109 • 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop General Description The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecting the J and K inputs together. Asynchronous Inputs: LOW input to SD (Set) sets Q to HIGH level LOW input to CD (Clear) sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH Features s ICC reduced by 50% s Outputs source/sink 24 mA s ACT109 has TTL-compatible inputs Ordering Code: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions FACT is a trademark of Fairchild Semiconductor Corporation. Order Number Package Number Package Description 74AC109SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74AC109SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74AC109MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74AC109PC N16E 16-Lead Plastic Dual-in-Line Package (PDIP), JEDEC MS-001, 0.300” Wide 74ACT109SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74AC109MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACT109PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Pin Names Description J1, J2, K1, K2 Data Inputs CP1, CP2 Clock Pulse Inputs CD1, CD2 Direct Clear Inputs SD1, SD2 Direct Set Inputs Q1, Q2, Q1, Q2 Outputs |
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