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74ACTQ18823MTD 데이터시트(PDF) 6 Page - Fairchild Semiconductor

부품명 74ACTQ18823MTD
상세설명  18-Bit D-Type Flip-Flop with 3-STATE Outputs
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제조업체  FAIRCHILD [Fairchild Semiconductor]
홈페이지  http://www.fairchildsemi.com
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6
Extended AC Electrical Characteristics
Note 11: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGH-
to-LOW (tOST).
Note 12: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (il.e., all LOW-to-
HIGH, HIGH-to-LOW, etc.).
Note 13: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load. This specification pertains to single output switching only.
Note 14: 3-STATE delays are load dominated and have been excluded from the datasheet.
Note 15: The Output Disable Time is dominated by the RC network (500
Ω, 250 pF) on the output and has been excluded from the datasheet.
Capacitance
Symbol
Parameter
TA = −40°C to +85°C
Units
VCC = Com
TA = −40°C to +85°C
CL = 50 pF
VCC = Com
16 Outputs Switching
CL = 250 pF
(Note 12)
(Note 13)
Min
Typ
Max
Min
Max
tPLH
Propagation Delay
5.2
6.5
7.6
7.0
9.8
ns
tPHL
CPn to On
5.3
6.5
7.8
6.8
10.0
tPHL
Propagation Delay
4.8
5.3
6.2
5.2
7.5
ns
CLRn to On
tPZH
Output Enable Time
4.2
4.8
6.5
(Note 14)
ns
tPZL
4.4
5.3
6.0
tPHZ
Output Disable Time
3.5
4.2
4.8
(Note 15)
ns
tPZL
4.6
5.2
6.0
tOSHL
Pin to Pin Skew
1.0
ns
(Note 11)
CPn to On
tOSLH
Pin to Pin Skew
1.0
ns
(Note 11)
CPn to On
tOSHL
Pin to Pin Skew
1.0
ns
(Note 11)
CLRn to Output
tOST
Pin to Pin Skew
1.5
ns
(Note 11)
CPn to Output
Symbol
Parameter
Typ
Units
Conditions
CIN
Input Pin Capacitance
4.5
pF
VCC = 5.0V
CPD
Power Dissipation Capacitance
95
pF
VCC = 5.0V


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