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FAN3241TMX 데이터시트(PDF) 2 Page - Fairchild Semiconductor |
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FAN3241TMX 데이터시트(HTML) 2 Page - Fairchild Semiconductor |
2 / 19 page © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3240 • Rev. 0.1.5 2 Ordering Information Part Number Minimum Input Time Maximum Pulse Width Package Packing Method Reel Quantity FAN3240TMX 15 ms 150 ms SOIC-8 Tape & Reel 2,500 FAN3241TMX 1 ms 30 ms SOIC-8 Tape & Reel 2,500 All standard Fairchild Semiconductor products are RoHS compliant and many are also “GREEN” or going green. For Fairchild’s definition of “green” please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. Package Outline Figure 2. SOIC-8 (Top View) Thermal Characteristics (1) Package ΘJL (2) ΘJT (3) ΘJA (4) ΨJB (5) ΨJT (6) Unit 8-Pin, Small-Outline Integrated Circuit (SOIC) 40 31 89 43 3.0 °C/W Notes: 1. Estimates derived from thermal simulation; actual values depend on the application. 2. Theta_JL ( ΘJL): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any thermal pad) that are typically soldered to a PCB. 3. Theta_JT ( ΘJT): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is held at a uniform temperature by a top-side heatsink. 4. Theta_JA (ΘJA): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow. The value given is for natural convection with no heatsink, as specified in JEDEC standards JESD51-2, JESD51-5, and JESD51-7, as appropriate. 5. Psi_JB ( ΨJB): Thermal characterization parameter providing correlation between semiconductor junction temperature and an application circuit board reference point for the thermal environment defined in Note 4. For the MLP-8 package, the board reference is defined as the PCB copper connected to the thermal pad and protruding from either end of the package. For the SOIC-8 package, the board reference is defined as the PCB copper adjacent to pin 6. 6. Psi_JT ( ΨJT): Thermal characterization parameter providing correlation between the semiconductor junction temperature and the center of the top of the package for the thermal environment defined in Note 4. |
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