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74F379SC 데이터시트(PDF) 2 Page - Fairchild Semiconductor

부품명 74F379SC
상세설명  Quad Parallel Register with Enable
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74F379SC 데이터시트(HTML) 2 Page - Fairchild Semiconductor

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Unit Loading/Fan Out
Functional Description
The 74F379 consists of four edge-triggered D-type flip-
flops with individual D inputs and Q and Q outputs. The
Clock (CP) and Enable (E) inputs are common to all flip-
flops. When the E is input HIGH, the register will retain the
present data independent of the CP input. The Dn and E
inputs can change when the clock is in either state, pro-
vided that the recommended setup and hold times are
observed.
Truth Table
H
= HIGH Voltage Level
L
= LOW Voltage Level
X
= Immaterial
 = LOW-to-HIGH Transition
NC
= No Change
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Pin Names
Description
U.L.
Input IIH/IIL
HIGH/LOW
Output IOH/IOL
E
Enable Input (Active LOW)
1.0/1.0
20
µA/−0.6 mA
D0–D3
Data Inputs
1.0/1.0
20
µA/−0.6 mA
CP
Clock Pulse Input (Active Rising Edge)
1.0/1.0
20
µA/−0.6 mA
Q0–Q3
Flip-Flop Outputs
50/33.3
−1 mA/20 mA
Q0–Q3
Complement Outputs
50/33.3
−1 mA/20 mA
Inputs
Outputs
E
CP
Dn
Qn
Qn
H

XNC
NC
L

HH
L
L

LL
H


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