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74F402 데이터시트(PDF) 2 Page - Fairchild Semiconductor |
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74F402 데이터시트(HTML) 2 Page - Fairchild Semiconductor |
2 / 9 page www.fairchildsemi.com 2 Unit Loading/Fan Out Note 1: Open Collector Functional Description The 74F402 Serial Data Polynomial Generator/Checker is an expandable 16-bit programmable device which oper- ates on serial data streams and provides a means of detecting transmission errors. Cyclic encoding and decod- ing schemes for error detection are based on polynomial manipulation in modulo arithmetic. For encoding, the data stream (message polynomial) is divided by a selected poly- nomial. This division results in a remainder (or residue) which is appended to the message as check bits. For error checking, the bit stream containing both data and check bits is divided by the same selected polynomial. If there are no detectable errors, this division results in a zero remain- der. Although it is possible to choose many generating polynomials of a given degree, standards exist that specify a small number of useful polynomials. The 74F402 imple- ments the polynomials listed in Table 1 by applying the appropriate logic levels to the select pins S0, S1, S2 and S3. The 74F402 consists of a 16-bit register, a Read Only Memory (ROM) and associated control circuitry as shown in the Block Diagram. The polynomial control code pre- sented at inputs S0, S1, S2 and S3 is decoded by the ROM, selecting the desired polynomial or part of a polynomial by establishing shift mode operation on the register with Exclusive OR (XOR) gates at appropriate inputs. To gener- ate the check bits, the data stream is entered via the Data Inputs (D), using the LOW-to-HIGH transition of the Clock Input (CP). This data is gated with the most significant Register Output (RO) via the Register Feedback Input (RFB), and controls the XOR gates. The Check Word Gen- erate (CWG) must be held HIGH while the data is being entered. After the last data bit is entered, the CWG is brought LOW and the check bits are shifted out of the reg- ister(s) and appended to the data bits (no external gating is needed). To check an incoming message for errors, both the data and check bits are entered through the D Input with the CWG Input held HIGH. The Error Output becomes valid after the last check bit has been entered into the ’F402 by a LOW-to-HIGH transition of CP, with the exception of the Ethernet polynomial (see Applications paragraph). If no detectable errors have occurred during the data transmis- sion, the resultant internal register bits are all LOW and the Error Output (ER) is HIGH. If a detectable error has occurred, ER is LOW. ER remains valid until the next LOW- to-HIGH transition of CP or until the device has been pre- set or reset. A HIGH on the Master Reset Input (MR) asynchronously clears the entire register. A LOW on the Preset Input (P) asynchronously sets the entire register with the exception of: 1. The Ethernet residue selection, in which the registers containing the non-zero residue are cleared; 2. The 56th order polynomial, in which the 8 least signifi- cant register bits of the least significant device are cleared; and, 3. Register S = 0, in which all bits are cleared. Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL S0–S3 Polynomial Select Inputs 1.0/0.67 20 µA/−0.4 mA CWG Check Word Generate Input 1.0/0.67 20 µA/−0.4 mA D/CW Serial Data/Check Word 285(100)/13.3(6.7) −5.7 mA(−2 mA)/8 mA (4 mA) D Data Input 1.0/0.67 20 µA/−0.4 mA ER Error Output (Note 1) /26.7(13.3) (Note 1) /16 mA (8 mA) RO Register Output 285(100)/13.3(6.7) −5.7 mA(−2 mA)/8 mA (4 mA) CP Clock Pulse 1.0/0.67 20 µA/−0.4 mA SEI Serial Expansion Input 1.0/0.67 20 µA/−0.4 mA RFB Register Feedback 1.0/0.67 20 µA/−0.4 mA MR Master Reset 1.0/0.67 20 µA/−0.4 mA P Preset 1.0/0.67 20 µA/−0.4 mA |
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