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74F433 데이터시트(PDF) 3 Page - Fairchild Semiconductor |
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74F433 데이터시트(HTML) 3 Page - Fairchild Semiconductor |
3 / 16 page 3 www.fairchildsemi.com Functional Description As shown in the block diagram, the 74F433 consists of three sections: 1. An Input Register with parallel and serial data inputs, as well as control inputs and outputs for input hand- shaking and expansion. 2. A 4-bit-wide, 62-word-deep fall-through stack with self- contained control logic. 3. An Output Register with parallel and serial data out- puts, as well as control inputs and outputs for output handshaking and expansion. These three sections operate asynchronously and are vir- tually independent of one another. Input Register (Data Entry) The Input Register can receive data in either bit-serial or 4- bit parallel form. It stores this data until it is sent to the fall- through stack, and also generates the necessary status and control signals. This 5-bit register (see Figure 1) is initialized by setting flip- flop F3 and resetting the other flip-flops. The Q-output of the last flip-flop (FC) is brought out as the Input Register Full (IRF) signal. After initialization, this output is HIGH. Parallel Entry—A HIGH on the Parallel Load (PL) input loads the D0–D3 inputs into the F0–F3 flip-flops and sets the FC flip-flop. This forces the IRF output LOW, indicating that the input register is full. During parallel entry, the Serial Input Clock (CPSI) input must be LOW. Serial Entry—Data on the Serial Data (DS) input is serially entered into the shift register (F3, F2, F1, F0, FC) on each HIGH-to-LOW transition of the CPSI input when the Serial Input Enable (IES) signal is LOW. During serial entry, the PL input should be LOW. After the fourth clock transition, the four data bits are located in flip-flops F0–F3. The FC flip-flop is set, forcing the IRF output LOW and internally inhibiting CPSI pulses from affecting the register. Figure 2 illustrates the final posi- tions in an 74F433 resulting from a 256-bit serial bit train (B0 is the first bit, B255 the last). FIGURE 1. Conceptual Input Section |
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