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74F524PC 데이터시트(PDF) 3 Page - Fairchild Semiconductor |
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74F524PC 데이터시트(HTML) 3 Page - Fairchild Semiconductor |
3 / 9 page 3 www.fairchildsemi.com Functional Description The 74F524 contains eight D-type flip-flops connected as a shift register with provision for either parallel or serial load- ing. Parallel data may be read from or loaded into the regis- ters via the data bus I/O0–I/O7. Serial data is entered from the C/SI input and may be shifted into the register and out through the C/SO output. Both parallel and serial data entry occur on the rising edge of the input clock (CP). The opera- tion of the shift register is controlled by two signals S0 and S1 according to the Select Truth Table. The 3-STATE paral- lel output buffers are enabled only in the Read mode. One port of an 8-bit comparator is attached to the data bus while the other port is tied to the outputs of the internal reg- ister. Three active-OFF, open-collector outputs indicate whether the contents held in the shift register are “greater than”, (GT), “less than” (LT), or “equal to” (EQ) the data on the input bus. A HIGH signal on the Status Enable (SE) input disables these outputs to the OFF state. A mode con- trol input (M) allows selection between a straightforward magnitude compare or a comparison between twos com- plement numbers. For “greater than” or “less than” detection, the C/SI input must be held HIGH, as indicated in the Status Truth Table. The internal logic is arranged such that a LOW signal on the C/SI input disables the “greater than” and “less than” outputs. The C/SO output will be forced HIGH if the “equal to” status condition exists, otherwise C/SO will be held LOW. These facilities enable the 74F524 to be cascaded for word length greater than eight bits. Word length expansion (in groups of eight bits) can be achieved by connecting the C/SO output of the more signif- icant byte to the C/SI input of the next less significant byte and also to its own SE input (see Figure 1). The C/SI input of the most significant device is held HIGH while the SE input of the least significant device is held LOW. The corre- sponding status outputs are AND-wired together. In the case of twos complement number compare, only the Mode input to the most significant device should be HIGH. The Mode inputs to all other cascaded devices are held LOW. Suppose that an inequality condition is detected in the most significant device. Assuming that the byte stored in the register is greater than the byte on the data bus, the EQ and LT outputs will be pulled LOW and the GT output will float HIGH. Also the C/SO output of the most significant device will be forced LOW, disabling the subsequent devices but enabling its own status outputs. The correct status condition is thus indicated. The same applies if the registered byte is less than the data byte, only in this case the EQ and GT outputs go LOW and LT output floats HIGH. If an equality condition is detected in the most significant device, its C/SO output is forced HIGH. This enables the next less significant device and also disables its own status outputs. In this way, the status output priority is handed down to the next less significant device which now effec- tively becomes the most significant byte. The worst case propagation delay for a compare operation involving “n” cascaded 74F524s will be when an equality condition is detected in all but the least significant byte. In this case, the status priority has to ripple all the way down the chain before the correct status output is established. Typically, this will take 35 + 6(n−2) ns. Function Diagram FIGURE 1. Cascading 74F524s for Comparing Longer Words |
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