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74LCX652 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 3 Page - Fairchild Semiconductor

๋ถ€ํ’ˆ๋ช… 74LCX652
์ƒ์„ธ๋‚ด์šฉ  Low Voltage Transceiver/Register with 5V Tolerant Inputs and Outputs
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์ œ์กฐ์‚ฌ  FAIRCHILD [Fairchild Semiconductor]
ํ™ˆํŽ˜์ด์ง€  http://www.fairchildsemi.com
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74LCX652 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 3 Page - Fairchild Semiconductor

 
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Functional Description
In the transceiver mode, data present at the HIGH imped-
ance port may be stored in either the A or B register or
both.
The select (SAB, SBA) controls can multiplex stored and
real-time.
The examples below demonstrate the four fundamental
bus-management functions that can be performed with the
Octal bus transceiver and receiver.
Data on the A or B data bus, or both can be stored in the
internal D flip-flop by LOW to HIGH transitions at the
appropriate Clock Inputs (CPAB, CPBA) regardless of the
Select or Output Enable Inputs. When SAB and SBA are in
the real time transfer mode, it is also possible to store data
without using the internal D flip-flops by simultaneously
enabling OEAB and OEBA. In this configuration each Out-
put reinforces its Input. Thus when all other data sources to
the two sets of bus lines are in a HIGH impedance state,
each set of bus lines will remain at its last state.
Real-Time Transfer
Bus B to Bus A
Real-Time Transfer
Bus A to Bus B
Transfer Storage
Data to A or B
Storage
OEAB
OEBA
CPAB CPBA SAB SBA
LL
X
X
X
L
OEAB OEBA CPAB CPBA SAB SBA
HH
X
X
L
X
OEAB
OEBA
CPAB CPBA SAB SBA
H
L
H or L H or L
H
H
OEAB
OEBA
CPAB CPBA SAB SBA
XH

XX
X
LX
X

XX
LH

XX


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