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74VCXH16374 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 6 Page - Fairchild Semiconductor

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์ƒ์„ธ๋‚ด์šฉ  Low Voltage 16-Bit D-Type Flip-Flop with Bushold
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6
AC Electrical Characteristics (Note 9)
Note 9: For CL 50PF, add approximately 300 ps to the AC maximum specification.
Note 10: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Symbol
Parameter
Conditions
VCC
TA 40qC to 85qC
Units
Figure
(V)
Min
Max
Number
fMAX
Maximum Clock Frequency
CL 30 pF
3.3
r 0.3
250
MHz
2.5
r 0.2
200
1.8
r 0.15
100
CL 15 pF
1.5
r 0.1
80.0
tPHL
Propagation Delay
CL pF, RL 500:
3.3
r 0.3
0.8
3.0
ns
Figures
1, 2
tPLH
2.5
r 0.2
1.0
3.9
1.8
r 0.15
1.5
7.8
CL 15 pF, RL 2 k:
1.5
r 0.1
1.0
15.6
Figures
7, 8
tPZL
Output Enable Time
CL 30 pF, RL 500:
3.3
r 0.3
0.8
3.5
ns
Figures
1, 3, 4
tPZH
2.5
r 0.2
1.0
4.6
1.8
r 0.15
1.5
9.2
CL 15 pF, RL 2 k:
1.5
r 0.1
1.0
18.4
Figures
7, 9, 10
tPLZ
Output Disable Time
CL 30 pF, RL 500:
3.3
r 0.3
0.8
3.5
ns
Figures
1, 3, 4
2.5
r 0.2
1.0
3.8
1.8
r 0.15
1.5
6.8
CL 15 pF, RL 2 k:
1.5
r 0.1
1.0
13.6
Figures
7, 9, 10
tS
Setup Time
CL 30 pF, RL 500:
3.3
r 0.3
1.5
ns
Figure 6
2.5
r 0.2
1.5
1.8
r 0.15
2.5
CL 15 pF, RL 500:
1.5
r 0.1
3.0
tH
Hold Time
CL 30 pF, RL 500:
3.3
r 0.3
1.0
ns
Figure 6
2.5
r 0.2
1.0
1.8
r 0.15
1.0
CL 15 pF, RL 500:
1.5
r 0.1
2.0
tW
Pulse Width
CL 30 pF, RL 500:
3.3
r 0.3
1.5
ns
Figure 5
2.5
r 0.2
1.5
1.8
r 0.15
4.0
CL 15 pF, RL 500:
1.5
r 0.1
4.0
tOSHL
Output to Output Skew
CL 30 pF, RL 500:
3.3
r 0.3
0.5
ns
tOSLH
(Note 10)
2.5
r 0.2
0.5
1.8
r 0.15
0.75
CL 15 pF, RL 2 k:
1.5
r 0.1
1.5


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