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74VHC374N 데이터시트(PDF) 5 Page - Fairchild Semiconductor |
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74VHC374N 데이터시트(HTML) 5 Page - Fairchild Semiconductor |
5 / 8 page ©1992 Fairchild Semiconductor Corporation www.fairchildsemi.com 74VHC374 Rev. 1.3 5 AC Electrical Characteristics Notes: 3. Parameter guaranteed by design. tOSLH = |tPLH max – tPLH min|; tOSHL = |tPHL max – tPHL min| 4. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr.) = CPD • VCC • fIN + ICC / 8 (per F/F). The total CPD when n pcs. of the Octal D Flip-Flop operates can be calculated by the equation: CPD (total) = 20 + 12n. AC Operating Requirements Symbol Parameter VCC (V) Conditions TA = 25°C TA = –40°C to +85°C Units Min. Typ. Max. Min. Max. tPLH, tPHL Propagation Delay Time (CP to On) 3.3 ± 0.3 CL = 15pF 8.1 12.7 1.0 15.0 ns CL = 50pF 10.6 16.2 1.0 18.5 5.0 ± 0.5 CL = 15pF 5.4 8.1 1.0 9.5 ns CL = 50pF 6.9 10.1 1.0 11.5 tPZL, tPZH 3-STATE Output Enable Time 3.3 ± 0.3 RL = 1kΩ CL = 15pF 7.1 11.0 1.0 13.0 ns CL = 50pF 9.6 14.5 1.0 16.5 5.0 ± 0.5 CL = 15pF 5.1 7.6 1.0 9.0 ns CL = 50pF 6.6 9.6 1.0 11.0 tPLZ, tPHZ 3-STATE Output Disable Time 3.3 ± 0.3 RL = 1kΩ CL = 50pF 10.2 14.0 1.0 16.0 ns 5.0 ± 0.5 CL = 50pF 6.1 8.8 1.0 10.0 tOSLH, tOSHL Output to Output Skew 3.3 ± 0.3 (3) CL = 50pF 1.5 1.5 ns 5.0 ± 0.5 CL = 50pF 1.0 1.0 fMAX Maximum Clock Frequency 3.3 ± 0.3 CL = 15pF 80 130 70 MHz CL = 50pF 55 85 50 5.0 ± 0.5 CL = 15pF 130 185 110 CL = 50pF 85 120 75 CIN Input Capacitance VCC = Open 4 10 10 pF COUT Output Capacitance VCC = 5.0V 6 pF CPD Power Dissipation Capacitance (4) 32 pF Symbol Parameter VCC (V) TA = 25°C TA = –40°C to +85°C Units Min. Typ. Max. Min. Max. tW(H), tW(L) Minimum Pulse Width (CP) 3.3 ± 0.3 5.0 5.5 ns 5.0 ± 0.5 5.0 5.0 tS Minimum Set-Up Time 3.3 ± 0.3 4.5 4.5 ns 5.0 ± 0.5 3.0 3.0 tH Minimum Hold Time 3.3 ± 0.3 2.0 2.0 ns 5.0 ± 0.5 2.0 2.0 |
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