MC14489B

MOTOROLA

2

BLOCK DIAGRAM

1

BitGrabber

CONFIGURATION REGISTER

8 BITS

Rx

DATA OUT

8

2

20

12

BitGrabber

DISPLAY REGISTER

24 BITS

NIBBLE MUX AND

DECODER ROM

ANODE DRIVERS

(CURRENT SOURCES)

BANK SWITCHES (FETs)

19

4

5

6

7

ab

DATA IN

c

d

e

f

g

h

24–1/2–STAGE

SHIFT REGISTER

11

10

7

4

4

4

4

4

4

4

4

4

4

4

4

18

POR

9

13

15

16

17

5

5

CLOCK

ENABLE

OSCILLATOR AND

CONTROL LOGIC

BANK 1 BANK 2 BANK 3 BANK 4 BANK 5

PIN 3 = VDD

PIN 14 = VSS

h

DIM/BRIGHT

BLANK

a TO g

D

C

Symbol

Parameter

Value

Unit

VDD

DC Supply Voltage

– 0.5 to + 6.0

V

Vin

DC Input Voltage

– 0.5 to VDD + 0.5

V

Vout

DC Output Voltage

– 0.5 to VDD + 0.5

V

Iin

DC Input Current — per Pin

(Includes Pin 8)

± 15

mA

Iout

DC Output Current —

Pins 1, 2, 4 – 7, 19, 20 Sourcing

Sinking

– 40

10

mA

Pins 9, 13, 15, 16, 17 Sinking

320

Pin 18

± 15

IDD, ISS DC Supply Current, VDD and VSS Pins

± 350

mA

TJ

Chip Junction Temperature

– 40 to + 130

°C

R

θJA

Device Thermal Resistance,

Junction–to–Ambient (see Thermal

Considerations section)

Plastic DIP

SOG Package

90

100

°C/W

Tstg

Storage Temperature

– 65 to + 150

°C

TL

Lead Temperature, 1 mm from Case for

10 Seconds

260

°C

* Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the limits in the Electrical Characteristics

tables or Pin Descriptions section.

This device contains protection circuitry to

guard against damage due to high static volt-

ages or electric fields. However, precautions

must be taken to avoid applications of any volt-

age higher than maximum rated voltages to this

high–impedance circuit. For proper operation,

Vin and Vout should be constrained to the range

VSS ≤ (Vin or Vout) ≤ VDD.

Unused inputs must always be tied to an ap-

propriate logic voltage level (e.g., either VSS or

VDD). Unused outputs must be left open.