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DM74LS166M 데이터시트(PDF) 2 Page - Fairchild Semiconductor |
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DM74LS166M 데이터시트(HTML) 2 Page - Fairchild Semiconductor |
2 / 6 page www.fairchildsemi.com 2 Function Table H = HIGH Level (steady state) L = LOW Level (steady state) X = Don’t Care (any input, including transitions) ↑ = Transition from LOW-to-HIGH level a…h = The level of steady-state input at inputs A through H, respectively QA0, QB0, QH0 = The level of QA, QB, QH, respectively, before the indicated steady-state input conditions were established QAn, QGn, = The level of QA, QG, respectively, before the most recent ↑ transition of the clock Logic Diagram Timing Diagram Typical Clear, Shift, Load, Inhibit and Shift Sequences Inputs Internal Output Clear Shift/ Clock Clock Serial Parallel Outputs QH Load Inhibit A…H QA QB L XXXXX L L L HX L L X X QA0 QB0 QH0 HL L ↑ X a…h abh HH L ↑ HX H QAn QGn HH L ↑ LX L QAn QGn HX H ↑ XX QA0 QB0 QH0 |
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