FAN5250

10

REV. 1.1.6 3/12/03

The switching frequency is primarily a function of:

1.

Spread between the two hysteretic thresholds

2.

3.

Output Inductor and Capacitor ESR

A transition back to PWM (Continuous Conduction Mode

or CCM) mode occurs when the inductor current has risen

sufficient as to be positive for 8 consecutive cycles. This

occurs when:

where

Because of the different control mechanisms, the value of the

load current where transition into CCM operation takes place

is typically higher compared to the load level at which transi-

tion into hysteretic mode had occurred. Hysteretic mode can

be disabled by setting the FPWM pin low. The presence of

this pin enhances applicability of the controller. Figure 6

shows an application circuit where hysteretic mode is only

allowed in a Deep Sleep Extension (DSX) mode. In this

mode the CPU has stopped and its current is significantly

lower compared to other modes of operation. Using the

FPWM pin simplifies control over converter modes of opera-

tion and increases efficiency.

Current Processing Section

The following discussion refers to Figure 7.

Active Droop

“Active Droop” or voltage positioning is now widely used in

the computer power applications. The technique is based on

raising the converter voltage at light load in anticipation of a

step increase in load current, and conversely, lowering

With Active Droop, the output voltage varies with the load as

if a resistor were connected in series with the converter’s out-

put, in other words, it's effect is to raise the output resistance

of the converter. To get the most from the Active Droop, its

magnitude should be scaled to match the output capacitor’s

ESR voltage drop.

Active Droop allows the size and cost of the output capaci-

tors required to handle CPU current transients to be reduced.

The reduction may be almost a factor of 2 when compared to

a system without Active Droop.

Figure 6. Allowing Hysteretic Mode in Deep Sleep

I

LOAD CCM

()

∆V

HYSTERESIS

2 ESR

-----------------------------------------

=

(7)

V

DROOP

I

MAX

ESR

×

=

(8)

START

DSX

ALTV

6

R8

R7

5

FPWM

Figure 7. Current Limit and Active Droop Circuits

LDRV

22

PGND

Q2

ISNS

21

in +

in –

2.5V

ILIM

det.

R

SENSE

I1A =

200K

16

SS

1.5M

14

C

SS

VCORE+

R

DROOP

V to I

EA Out

DAC and

Soft Start

17pf

100K

300K

ISNS

48

I1B =

ISNS

8

I2 =

4 * ILIM

3

15

ILIM

1.2V

R

ILIM

ILIM mirror

S/H