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FAN5250QSCX 데이터시트(PDF) 11 Page - Fairchild Semiconductor

부품명 FAN5250QSCX
상세설명  Mobile Processor Core-Voltage Regulator
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제조업체  FAIRCHILD [Fairchild Semiconductor]
홈페이지  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

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FAN5250
REV. 1.1.6 3/12/03
11
Figure 8. Active Droop
Additionally, the CPU power dissipation is also slightly
reduced as it is proportional to the applied voltage squared
and even slight voltage decrease translates to a measurable
reduction in power dissipated.
Figure 9. Effect of Active Droop on ESR
The Crusoe
 processor regulation window including
transients is specified as +5%…–2%. To accommodate the
droop, the output voltage of the converter is raised by about
3.25% at no load as shown below (R24 = 1K and
R25 = 30.1K):
Figure 10. Setting the No-Load Output Voltage Rise
The converter response to the load step is shown in Figure
11. At zero load current, the output voltage is raised ~50mV
above nominal value of 1.35V. When the load current
increases, the output voltage droops down approximately
55mV. Due to use of Active Droop, the converter’s output
voltage adaptively changes with the load current allowing
better utilization of the regulation window.
Figure 11. Converter Response to 5A Load Step
The current through RSENSE resistor (ISNS) is sampled
shortly after Q2 is turned on. That current is held, and then
injected (with a 1/48 gain) into the inverting path of the error
amp to produce an offset to the sensed output voltage at
VCORE + proportional to the load current.
Setting the Current Limit
A ratio of ISNS is also compared to the current established
when a 1.2 V internal reference drives the ILIM pin. The
threshold is determined at the point when the
Since
therefore,
Since the tolerance on the current limit is largely dependent
on the ratio of the external resistors it is fairly accurate if the
voltage drop on the Switching Node side of RSENSE is an
accurate representation of the load current. When using the
MOSFET as the sensing element, the variation of RDS(ON)
causes proportional variation in the ISNS. This value not
only varies from device to device, but also has a typical
junction temperature coefficient of about 0.4%/°C
(consult the MOSFET datasheet for actual values), so the
actual current limit set point will decrease proportional to
increasing MOSFET die temperature. The same discussion
applies to the VDROOP calculation, which has an additional
initial error of ±20% due to its value being determined by
a ratio between RSENSE and the internal 100K resistor.
1.2
I
LOAD
V
DROOP
I
MAX
V
ESR
upper lim
lower lim
ILOAD
Vout
(no droop)
Vout
droop » ESR
upper lim
lower lim
V
ESR
16 VCORE+
V CORE
R24
R25
C
OUT
1
2
ICPU = 0A...5.0A
lower limit
VCPU = 1.35V
upper limit
Ch2 2.0A
M50
µs
Ch1 50mV
V
DROOP
100K
I
LOAD
R
DS ON
()
×
48
R
SENSE
×
--------------------------------------------
×
=
V
DROOP
2083
I
LOAD
R
DS ON
()
×
R
SENSE
--------------------------------------------
×
=
(9a)
(9b)
ISNS
8
---------------
ILIM
4
×
3
----------------------
>
ISNS
I
LOAD
R
DS ON
()
×
R
SENSE
--------------------------------------------
=
I
LIMIT
1.2V
R
LIM
-------------
4
3
---
8
100
R
SENSE
+
()
×
R
DS ON
()
----------------------------------------------------
×
×
=
(10)


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