ADF4108S

ASD0016548 Rev. A | Page 10 of 21

RF INPUT STAGE

The RF input stage is shown in Figure 5. It is followed by a two-stage limiting amplifier to generate the CML clock

levels needed for the prescaler.

Figure 5. Reference Input Stage

PRESCALER (P/P + 1)

The dual-modulus prescaler (P/P + 1), along with the A and B counters, enables the large division ratio, N, to be realized (N

= BP + A). The dual-modulus prescaler, operating at CML levels, takes the clock from the RF input stage and divides it

down to a manageable frequency for the CMOS A and B counters. The prescaler is programmable. It can be set in software

to 8/9, 16/17, 32/33, or 64/65. It is based on a synchronous 4/5 core. A minimum divide ratio is possible for contiguous

output frequencies. This minimum is determined by P, the prescaler value, and is given by (P

A AND B COUNTERS

The A and B CMOS counters combine with the dual-modulus prescaler to allow a wide ranging division ratio in the PLL

feedback counter. The counters are specified to work when the prescaler output is 300 MHz or less. Thus, with an RF input

frequency of 4.0 GHz, a prescaler value of 16/17 is valid but a value of 8/9 is not valid.

Pulse Swallow Function

The A and B counters, in conjunction with the dual-modulus prescaler, make it possible to generate output frequencies that

are spaced only by the reference frequency divided by R. The equation for the VCO frequency is as follows:

Where:

f

oscillator (VCO).

P is the preset modulus of dual-modulus prescaler (8/9,

16/17, and so on.).

B is the preset divide ratio of binary 13-bit counter (3 to

8191). A is the preset divide ratio of binary 6-bit swallow

counter (0 to 63).

Figure 6. A and B Counters