AD5551BR datasheet(4/16 Pages) AD

부품명	AD5551BR

상세설명	2.7 V to 5.5 V, Serial-Input, Voltage-Output, 14-Bit DACs

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AD5551/AD5552

Rev. A | Page 4 of 16

TIMING CHARACTERISTICS

VDD = 2.7 V to 5.5 V, 2.5 V ≤ VREF ≤ 5.5 V, AGND = DGND = 0 V. All specifications −40°C ≤ TA ≤ +85°C, unless otherwise noted.

Table 2.

Limit at TMIN, TMAX

Parameter1, 2

All Versions

Unit

Description

fSCLK

25

MHz max

SCLK cycle frequency

t1

40

ns min

SCLK cycle time

t2

20

ns min

SCLK high time

t3

20

ns min

SCLK low time

t4

15

ns min

CS low to SCLK high setup

t5

15

ns min

CS high to SCLK high setup

t6

35

ns min

SCLK high to CS low hold time

t7

20

ns min

SCLK high to CS high hold time

t8

15

ns min

Data setup time

t9

0

ns min

Data hold time

t10

30

ns min

LDAC pulse width

t11

30

ns min

CS high to LDAC low setup

t12

30

ns min

CS high time between active periods

1 Guaranteed by design, not production tested.

2 Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 5 ns (10% to

90% of +3 V and timed from a voltage level of +1.6 V).

SCLK

CS

DIN

LDAC*

DB13

DB0

t6

t4

t12

t8

t9

t2

t3

t1

t7

t5

t10

t11

*AD5552 ONLY. MAY BE TIED PERMANENTLY LOW IF REQUIRED.

Figure 3. Timing Diagram

유사한 부품 번호 - AD5551BR

제조업체	부품명	데이터시트	상세설명
Analog Devices	AD5551BR	208Kb / 12P	5 V, Serial-Input Voltage-Output, 14-Bit DACs REV. 0

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AD5551BR 데이터시트(PDF) 4 Page - Analog Devices

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